Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	222994	1		T5	82		T6	61		T7	3
full_word	530680	1		T5	39		T6	37		T7	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	753384	1		T5	121		T6	98		T7	9
auto[TlIntgErrCmd]	99	1		T105	5		T106	3		T107	7
auto[TlIntgErrData]	82	1		T105	6		T106	5		T107	5
auto[TlIntgErrBoth]	109	1		T105	9		T106	2		T107	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	462327	1		T5	8		T6	14		T7	8
auto[1]	291347	1		T5	113		T6	84		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	186018	1		T5	5		T6	6		T7	2
auto[TlIntgErrNone]	partial	auto[1]	36712	1		T5	77		T6	55		T7	1
auto[TlIntgErrNone]	full_word	auto[0]	276182	1		T5	3		T6	8		T7	6
auto[TlIntgErrNone]	full_word	auto[1]	254472	1		T5	36		T6	29		T8	11
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T105	1		T107	4		T109	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T105	4		T106	3		T107	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T110	1		T112	1		T55	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T107	2		T109	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T105	5		T106	1		T107	2
auto[TlIntgErrData]	partial	auto[1]	32	1		T106	4		T107	2		T109	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T105	1		T107	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T111	1		T55	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T105	2		T106	1		T107	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T105	6		T106	1		T107	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T105	1		T113	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T55	1		T115	1		T116	1