Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.64	100.00	55.32	85.38		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	32541005	12001	0	0
late_debug_enable_rd_A	32541005	2820	0	0
late_debug_enable_regwen_rd_A	32541005	4002	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32541005	12001	0	0
T23	406325	16	0	0
T24	135040	1461	0	0
T25	292990	63	0	0
T27	71942	4	0	0
T28	8365	17	0	0
T67	195532	32	0	0
T68	660620	125	0	0
T69	20512	733	0	0
T70	26716	40	0	0
T71	461428	145	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32541005	2820	0	0
T23	406325	3	0	0
T25	292990	73	0	0
T28	8365	21	0	0
T30	39462	31	0	0
T59	10244	8	0	0
T69	20512	185	0	0
T79	26172	13	0	0
T82	7940	8	0	0
T102	686919	56	0	0
T103	23135	49	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32541005	4002	0	0
T23	406325	12	0	0
T25	292990	45	0	0
T30	39462	55	0	0
T69	20512	213	0	0
T79	26172	21	0	0
T81	27585	31	0	0
T82	7940	6	0	0
T102	686919	78	0	0
T103	23135	18	0	0
T104	186222	582	0	0