Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
1 | 1 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
11014314 |
11013624 |
0 |
0 |
selKnown1 |
12396334 |
12395644 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11014314 |
11013624 |
0 |
0 |
T1 |
362 |
360 |
0 |
0 |
T2 |
312 |
310 |
0 |
0 |
T3 |
306 |
304 |
0 |
0 |
T4 |
350 |
348 |
0 |
0 |
T5 |
242486 |
242482 |
0 |
0 |
T6 |
157645 |
157641 |
0 |
0 |
T7 |
3070 |
3066 |
0 |
0 |
T8 |
114475 |
114471 |
0 |
0 |
T9 |
0 |
25 |
0 |
0 |
T10 |
0 |
27 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T18 |
352 |
348 |
0 |
0 |
T19 |
376 |
372 |
0 |
0 |
T20 |
25 |
23 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T22 |
0 |
40 |
0 |
0 |
T32 |
2 |
0 |
0 |
0 |
T50 |
2 |
0 |
0 |
0 |
T51 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12396334 |
12395644 |
0 |
0 |
T1 |
2341 |
2339 |
0 |
0 |
T2 |
1997 |
1995 |
0 |
0 |
T3 |
2153 |
2151 |
0 |
0 |
T4 |
1434 |
1432 |
0 |
0 |
T5 |
480886 |
480882 |
0 |
0 |
T6 |
313487 |
313483 |
0 |
0 |
T7 |
3377 |
3373 |
0 |
0 |
T8 |
326948 |
326944 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
6 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T18 |
2305 |
2301 |
0 |
0 |
T19 |
1354 |
1350 |
0 |
0 |
T20 |
22 |
20 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T22 |
0 |
40 |
0 |
0 |
T32 |
2 |
0 |
0 |
0 |
T50 |
2 |
0 |
0 |
0 |
T51 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
1 | 1 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
608617 |
608547 |
0 |
0 |
selKnown1 |
1990802 |
1990732 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
608617 |
608547 |
0 |
0 |
T1 |
181 |
180 |
0 |
0 |
T2 |
156 |
155 |
0 |
0 |
T3 |
153 |
152 |
0 |
0 |
T4 |
175 |
174 |
0 |
0 |
T5 |
121241 |
121240 |
0 |
0 |
T6 |
78600 |
78599 |
0 |
0 |
T7 |
1534 |
1533 |
0 |
0 |
T8 |
56185 |
56184 |
0 |
0 |
T18 |
175 |
174 |
0 |
0 |
T19 |
187 |
186 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1990802 |
1990732 |
0 |
0 |
T1 |
2160 |
2159 |
0 |
0 |
T2 |
1841 |
1840 |
0 |
0 |
T3 |
2000 |
1999 |
0 |
0 |
T4 |
1259 |
1258 |
0 |
0 |
T5 |
359641 |
359640 |
0 |
0 |
T6 |
234449 |
234448 |
0 |
0 |
T7 |
1841 |
1840 |
0 |
0 |
T8 |
268674 |
268673 |
0 |
0 |
T18 |
2128 |
2127 |
0 |
0 |
T19 |
1165 |
1164 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
1 | 1 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
203 |
133 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
12 |
11 |
0 |
0 |
T9 |
0 |
11 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
14 |
13 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
181 |
111 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
5 |
4 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
3 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
11 |
10 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
1 | 1 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10403980 |
10403705 |
0 |
0 |
selKnown1 |
10403980 |
10403705 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10403980 |
10403705 |
0 |
0 |
T1 |
181 |
180 |
0 |
0 |
T2 |
156 |
155 |
0 |
0 |
T3 |
153 |
152 |
0 |
0 |
T4 |
175 |
174 |
0 |
0 |
T5 |
121241 |
121240 |
0 |
0 |
T6 |
79026 |
79025 |
0 |
0 |
T7 |
1534 |
1533 |
0 |
0 |
T8 |
58264 |
58263 |
0 |
0 |
T18 |
175 |
174 |
0 |
0 |
T19 |
187 |
186 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10403980 |
10403705 |
0 |
0 |
T1 |
181 |
180 |
0 |
0 |
T2 |
156 |
155 |
0 |
0 |
T3 |
153 |
152 |
0 |
0 |
T4 |
175 |
174 |
0 |
0 |
T5 |
121241 |
121240 |
0 |
0 |
T6 |
79026 |
79025 |
0 |
0 |
T7 |
1534 |
1533 |
0 |
0 |
T8 |
58264 |
58263 |
0 |
0 |
T18 |
175 |
174 |
0 |
0 |
T19 |
187 |
186 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T8 |
1 | 1 | Covered | T6,T8 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1514 |
1239 |
0 |
0 |
selKnown1 |
1371 |
1096 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1514 |
1239 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
13 |
12 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
14 |
13 |
0 |
0 |
T9 |
0 |
14 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
11 |
10 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1371 |
1096 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
5 |
4 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
3 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T20 |
11 |
10 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |