SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
47.72 | 72.55 | 33.33 | 28.57 | 54.17 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 420 | 420 | 0 | 0 |
OutputsKnown_A | 11944812 | 11872812 | 0 | 0 |
gen_flops.OutputDelay_A | 5972406 | 5934777 | 0 | 630 |
gen_no_flops.OutputDelay_A | 5972406 | 5936406 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 420 | 420 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T18 | 6 | 6 | 0 | 0 |
T19 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11944812 | 11872812 | 0 | 0 |
T1 | 12960 | 12552 | 0 | 0 |
T2 | 11046 | 10734 | 0 | 0 |
T3 | 12000 | 11694 | 0 | 0 |
T4 | 7554 | 7254 | 0 | 0 |
T5 | 2157846 | 2156874 | 0 | 0 |
T6 | 1406694 | 1404492 | 0 | 0 |
T7 | 11046 | 10740 | 0 | 0 |
T8 | 1612044 | 1610130 | 0 | 0 |
T18 | 12768 | 12432 | 0 | 0 |
T19 | 6990 | 6618 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5972406 | 5934777 | 0 | 630 |
T1 | 6480 | 6267 | 0 | 9 |
T2 | 5523 | 5358 | 0 | 9 |
T3 | 6000 | 5838 | 0 | 9 |
T4 | 3777 | 3618 | 0 | 9 |
T5 | 1078923 | 1078419 | 0 | 9 |
T6 | 703347 | 702192 | 0 | 9 |
T7 | 5523 | 5361 | 0 | 9 |
T8 | 806022 | 805020 | 0 | 9 |
T18 | 6384 | 6207 | 0 | 9 |
T19 | 3495 | 3300 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5972406 | 5936406 | 0 | 0 |
T1 | 6480 | 6276 | 0 | 0 |
T2 | 5523 | 5367 | 0 | 0 |
T3 | 6000 | 5847 | 0 | 0 |
T4 | 3777 | 3627 | 0 | 0 |
T5 | 1078923 | 1078437 | 0 | 0 |
T6 | 703347 | 702246 | 0 | 0 |
T7 | 5523 | 5370 | 0 | 0 |
T8 | 806022 | 805065 | 0 | 0 |
T18 | 6384 | 6216 | 0 | 0 |
T19 | 3495 | 3309 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1990802 | 1978802 | 0 | 0 |
gen_flops.OutputDelay_A | 1990802 | 1978259 | 0 | 210 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978259 | 0 | 210 |
T1 | 2160 | 2089 | 0 | 3 |
T2 | 1841 | 1786 | 0 | 3 |
T3 | 2000 | 1946 | 0 | 3 |
T4 | 1259 | 1206 | 0 | 3 |
T5 | 359641 | 359473 | 0 | 3 |
T6 | 234449 | 234064 | 0 | 3 |
T7 | 1841 | 1787 | 0 | 3 |
T8 | 268674 | 268340 | 0 | 3 |
T18 | 2128 | 2069 | 0 | 3 |
T19 | 1165 | 1100 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1990802 | 1978802 | 0 | 0 |
gen_flops.OutputDelay_A | 1990802 | 1978259 | 0 | 210 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978259 | 0 | 210 |
T1 | 2160 | 2089 | 0 | 3 |
T2 | 1841 | 1786 | 0 | 3 |
T3 | 2000 | 1946 | 0 | 3 |
T4 | 1259 | 1206 | 0 | 3 |
T5 | 359641 | 359473 | 0 | 3 |
T6 | 234449 | 234064 | 0 | 3 |
T7 | 1841 | 1787 | 0 | 3 |
T8 | 268674 | 268340 | 0 | 3 |
T18 | 2128 | 2069 | 0 | 3 |
T19 | 1165 | 1100 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1990802 | 1978802 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1990802 | 1978802 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1990802 | 1978802 | 0 | 0 |
gen_flops.OutputDelay_A | 1990802 | 1978259 | 0 | 210 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978259 | 0 | 210 |
T1 | 2160 | 2089 | 0 | 3 |
T2 | 1841 | 1786 | 0 | 3 |
T3 | 2000 | 1946 | 0 | 3 |
T4 | 1259 | 1206 | 0 | 3 |
T5 | 359641 | 359473 | 0 | 3 |
T6 | 234449 | 234064 | 0 | 3 |
T7 | 1841 | 1787 | 0 | 3 |
T8 | 268674 | 268340 | 0 | 3 |
T18 | 2128 | 2069 | 0 | 3 |
T19 | 1165 | 1100 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1990802 | 1978802 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1990802 | 1978802 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1990802 | 1978802 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1990802 | 1978802 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1990802 | 1978802 | 0 | 0 |
T1 | 2160 | 2092 | 0 | 0 |
T2 | 1841 | 1789 | 0 | 0 |
T3 | 2000 | 1949 | 0 | 0 |
T4 | 1259 | 1209 | 0 | 0 |
T5 | 359641 | 359479 | 0 | 0 |
T6 | 234449 | 234082 | 0 | 0 |
T7 | 1841 | 1790 | 0 | 0 |
T8 | 268674 | 268355 | 0 | 0 |
T18 | 2128 | 2072 | 0 | 0 |
T19 | 1165 | 1103 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |