Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T1,*T3,*T4 |
Yes |
T1,T3,T5 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T5 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T1,T3,T8 |
Yes |
T1,T3,T4 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T3,T4 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
260 |
150 |
57.69 |
Total Bits 0->1 |
130 |
76 |
58.46 |
Total Bits 1->0 |
130 |
74 |
56.92 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
260 |
150 |
57.69 |
Port Bits 0->1 |
130 |
76 |
58.46 |
Port Bits 1->0 |
130 |
74 |
56.92 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[3:0] |
Yes |
Yes |
*T4,*T5,*T7 |
Yes |
T5,T8,T12 |
INPUT |
data_i[56:4] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T8,T12,T54 |
Yes |
T4,T8,T19 |
INPUT |
data_o[5:0] |
Yes |
Yes |
*T4,*T5,*T7 |
Yes |
T5,T8,T12 |
OUTPUT |
data_o[6] |
No |
No |
|
No |
|
OUTPUT |
data_o[31:7] |
Yes |
Yes |
*T55,*T56,*T57 |
Yes |
T55,T56,T58 |
OUTPUT |
data_o[32] |
No |
No |
|
Yes |
T59 |
OUTPUT |
data_o[53:33] |
Yes |
Yes |
*T12,*T60,*T55 |
Yes |
T12,T60,T55 |
OUTPUT |
data_o[54] |
No |
No |
|
Yes |
T12,T61 |
OUTPUT |
data_o[56:55] |
Yes |
Yes |
T8,T62,T63 |
Yes |
T8,T62,T63 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T8,T12,T54 |
Yes |
T4,T8,T42 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T5,T8,T12 |
Yes |
T4,T5,T8 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T1,*T3,*T19 |
Yes |
T1,T3,T19 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T3,T19 |
Yes |
T1,T3,T19 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T1,T3,T19 |
Yes |
T1,T3,T19 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T3,T19 |
Yes |
T1,T3,T19 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T5,*T6,*T7 |
Yes |
T5,T6,T18 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T18 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T18 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T8,T20,T10 |
Yes |
T1,T18,T8 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T5,T6,T18 |
Yes |
T5,T6,T8 |
OUTPUT |
*Tests covering at least one bit in the range