Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202734	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	574406	1		T5	6		T6	15		T7	37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	479374	1		T5	8		T6	12		T7	14
values[0x0]	146763	1		T5	1		T6	12		T7	31
values[0x1]	151003	1		T6	19		T7	38		T8	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155490	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	621650	1		T5	8		T6	22		T7	44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2669	1		T15	2		T32	1		T28	2
valid_sources[0x01]	3169	1		T15	1		T11	1		T27	4
valid_sources[0x02]	3743	1		T27	3		T68	11		T72	257
valid_sources[0x03]	3539	1		T11	3		T32	316		T27	2
valid_sources[0x04]	2514	1		T11	1		T32	19		T27	13
valid_sources[0x05]	3392	1		T11	1		T27	7		T68	1
valid_sources[0x06]	2897	1		T15	1		T27	8		T68	2
valid_sources[0x07]	2265	1		T32	6		T27	3		T68	11
valid_sources[0x08]	2853	1		T7	3		T11	1		T32	10
valid_sources[0x09]	3514	1		T32	3		T68	2		T72	267
valid_sources[0x0a]	4009	1		T15	1		T27	4		T72	287
valid_sources[0x0b]	2962	1		T7	2		T27	1		T68	2
valid_sources[0x0c]	2540	1		T32	24		T27	1		T68	17
valid_sources[0x0d]	3666	1		T6	1		T9	2		T32	24
valid_sources[0x0e]	3032	1		T7	1		T11	1		T32	34
valid_sources[0x0f]	3456	1		T7	1		T27	2		T68	13
valid_sources[0x10]	2872	1		T9	2		T27	2		T28	1
valid_sources[0x11]	3215	1		T15	1		T32	10		T28	12
valid_sources[0x12]	2868	1		T7	2		T15	1		T27	3
valid_sources[0x13]	3479	1		T28	21		T68	4		T72	232
valid_sources[0x14]	2340	1		T27	1		T28	6		T68	6
valid_sources[0x15]	2810	1		T6	4		T15	1		T28	14
valid_sources[0x16]	2466	1		T15	2		T27	4		T28	6
valid_sources[0x17]	2988	1		T26	1		T32	29		T27	5
valid_sources[0x18]	2493	1		T7	4		T9	3		T27	1
valid_sources[0x19]	2997	1		T7	1		T15	1		T32	24
valid_sources[0x1a]	3331	1		T11	1		T32	3		T27	1
valid_sources[0x1b]	2957	1		T26	1		T27	4		T68	2
valid_sources[0x1c]	3241	1		T9	8		T32	62		T27	1
valid_sources[0x1d]	3268	1		T11	1		T27	4		T68	8
valid_sources[0x1e]	3005	1		T11	2		T27	2		T68	2
valid_sources[0x1f]	3073	1		T7	2		T27	4		T28	13
valid_sources[0x20]	3047	1		T26	1		T27	1		T68	2
valid_sources[0x21]	2916	1		T32	2		T27	4		T28	2
valid_sources[0x22]	2823	1		T15	1		T27	3		T72	277
valid_sources[0x23]	2881	1		T15	1		T11	1		T32	275
valid_sources[0x24]	2532	1		T32	8		T27	3		T28	9
valid_sources[0x25]	2830	1		T15	1		T68	8		T72	220
valid_sources[0x26]	3862	1		T7	1		T11	1		T28	21
valid_sources[0x27]	2781	1		T32	35		T28	2		T68	1
valid_sources[0x28]	3707	1		T6	1		T7	1		T72	292
valid_sources[0x29]	2738	1		T11	1		T32	26		T27	2
valid_sources[0x2a]	2456	1		T11	1		T26	1		T32	3
valid_sources[0x2b]	2851	1		T27	5		T68	2		T72	254
valid_sources[0x2c]	2705	1		T32	21		T28	1		T68	4
valid_sources[0x2d]	3166	1		T32	20		T27	11		T28	8
valid_sources[0x2e]	2390	1		T7	1		T27	4		T68	16
valid_sources[0x2f]	3027	1		T32	19		T27	5		T28	8
valid_sources[0x30]	3144	1		T9	1		T32	44		T68	6
valid_sources[0x31]	2986	1		T27	6		T28	15		T68	2
valid_sources[0x32]	3292	1		T6	1		T27	1		T28	16
valid_sources[0x33]	2934	1		T27	2		T68	2		T72	280
valid_sources[0x34]	2744	1		T15	2		T11	1		T27	2
valid_sources[0x35]	2648	1		T7	1		T32	7		T68	8
valid_sources[0x36]	2661	1		T7	2		T15	1		T32	7
valid_sources[0x37]	3217	1		T32	2		T27	3		T28	8
valid_sources[0x38]	3070	1		T6	4		T32	38		T27	2
valid_sources[0x39]	2822	1		T32	24		T68	6		T72	252
valid_sources[0x3a]	2958	1		T27	3		T28	1		T68	14
valid_sources[0x3b]	2736	1		T27	6		T28	9		T68	6
valid_sources[0x3c]	3828	1		T11	1		T32	3		T27	3
valid_sources[0x3d]	2743	1		T11	1		T27	13		T28	2
valid_sources[0x3e]	3138	1		T15	1		T32	12		T28	2
valid_sources[0x3f]	3664	1		T15	1		T11	1		T32	3
valid_sources[0x40]	2556	1		T6	2		T7	1		T15	1
valid_sources[0x41]	3316	1		T6	4		T27	1		T28	2
valid_sources[0x42]	3175	1		T7	1		T27	4		T28	3
valid_sources[0x43]	3686	1		T7	2		T15	1		T27	3
valid_sources[0x44]	3225	1		T32	12		T27	1		T28	14
valid_sources[0x45]	3600	1		T8	9		T32	21		T27	1
valid_sources[0x46]	3211	1		T7	1		T32	21		T27	6
valid_sources[0x47]	3717	1		T6	2		T15	1		T27	3
valid_sources[0x48]	3884	1		T7	1		T15	2		T27	3
valid_sources[0x49]	3664	1		T15	1		T27	9		T28	3
valid_sources[0x4a]	3383	1		T7	2		T15	1		T26	1
valid_sources[0x4b]	2925	1		T32	11		T27	4		T28	2
valid_sources[0x4c]	2476	1		T15	1		T26	1		T32	3
valid_sources[0x4d]	3687	1		T32	296		T27	3		T28	15
valid_sources[0x4e]	3209	1		T27	4		T68	9		T72	276
valid_sources[0x4f]	3367	1		T7	1		T11	1		T26	1
valid_sources[0x50]	3309	1		T7	1		T32	37		T27	4
valid_sources[0x51]	2500	1		T15	1		T27	3		T28	6
valid_sources[0x52]	3436	1		T7	1		T32	25		T27	3
valid_sources[0x53]	3225	1		T32	19		T28	3		T68	4
valid_sources[0x54]	3793	1		T7	1		T32	39		T27	2
valid_sources[0x55]	3089	1		T15	1		T9	2		T32	4
valid_sources[0x56]	2725	1		T7	1		T15	1		T28	2
valid_sources[0x57]	3187	1		T15	1		T9	3		T27	7
valid_sources[0x58]	2416	1		T9	2		T11	1		T28	6
valid_sources[0x59]	2945	1		T32	19		T27	2		T28	14
valid_sources[0x5a]	2557	1		T27	5		T68	2		T72	256
valid_sources[0x5b]	2425	1		T6	1		T7	1		T15	2
valid_sources[0x5c]	2876	1		T15	1		T9	1		T27	2
valid_sources[0x5d]	2933	1		T11	1		T27	4		T28	2
valid_sources[0x5e]	2571	1		T7	1		T15	1		T28	3
valid_sources[0x5f]	2919	1		T15	1		T26	1		T32	11
valid_sources[0x60]	2995	1		T15	1		T11	1		T32	21
valid_sources[0x61]	2747	1		T7	2		T32	58		T68	13
valid_sources[0x62]	3402	1		T27	5		T28	2		T68	9
valid_sources[0x63]	3466	1		T6	1		T27	1		T68	15
valid_sources[0x64]	3739	1		T15	2		T68	1		T72	265
valid_sources[0x65]	2341	1		T15	2		T27	9		T28	4
valid_sources[0x66]	2522	1		T32	41		T27	2		T28	3
valid_sources[0x67]	3023	1		T7	1		T9	1		T11	1
valid_sources[0x68]	3173	1		T68	2		T72	287		T61	2
valid_sources[0x69]	2918	1		T32	11		T27	1		T28	5
valid_sources[0x6a]	3192	1		T11	1		T27	1		T68	6
valid_sources[0x6b]	2640	1		T7	1		T68	6		T72	260
valid_sources[0x6c]	3006	1		T32	9		T27	1		T28	19
valid_sources[0x6d]	2234	1		T15	1		T26	1		T27	6
valid_sources[0x6e]	2748	1		T28	1		T68	5		T72	243
valid_sources[0x6f]	2631	1		T32	18		T27	4		T68	3
valid_sources[0x70]	3003	1		T32	38		T27	5		T28	18
valid_sources[0x71]	3326	1		T7	1		T15	1		T27	2
valid_sources[0x72]	3436	1		T11	1		T26	1		T32	292
valid_sources[0x73]	3164	1		T7	1		T15	2		T32	851
valid_sources[0x74]	2807	1		T15	1		T32	18		T27	2
valid_sources[0x75]	3818	1		T5	9		T32	31		T27	2
valid_sources[0x76]	2953	1		T32	10		T27	2		T28	10
valid_sources[0x77]	3128	1		T15	2		T11	1		T27	1
valid_sources[0x78]	3839	1		T7	1		T15	1		T9	1
valid_sources[0x79]	2829	1		T26	2		T32	274		T27	2
valid_sources[0x7a]	2852	1		T7	1		T32	1		T27	4
valid_sources[0x7b]	3038	1		T27	3		T28	12		T68	6
valid_sources[0x7c]	3315	1		T15	1		T27	2		T28	19
valid_sources[0x7d]	2502	1		T7	1		T11	1		T27	2
valid_sources[0x7e]	2990	1		T11	1		T32	12		T28	6
valid_sources[0x7f]	2759	1		T7	1		T15	1		T32	5
valid_sources[0x80]	3288	1		T15	1		T32	57		T27	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

284519

1

T5

5

T6

3

T7

9

values[0x0]

all_enables

biggest_size

145034

1

T5

1

T6

7

T7

12

values[0x1]

all_enables

biggest_size

144853

1

T6

5

T7

16

T9

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4496	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19648	1		T1	3		T2	1		T3	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8840	1		T26	24		T32	32		T27	134
values[0x0]	7567	1		T1	4		T2	5		T3	6
values[0x1]	7737	1		T1	8		T2	2		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3442	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20702	1		T1	5		T2	1		T3	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	123	1		T26	8		T32	1		T28	1
valid_sources[0x01]	100	1		T26	5		T69	1		T71	1
valid_sources[0x02]	63	1		T68	9		T69	1		T71	3
valid_sources[0x03]	118	1		T123	1		T27	4		T69	1
valid_sources[0x04]	79	1		T27	22		T68	6		T69	1
valid_sources[0x05]	92	1		T33	3		T44	1		T27	5
valid_sources[0x06]	78	1		T2	1		T68	7		T71	3
valid_sources[0x07]	91	1		T28	2		T68	2		T50	11
valid_sources[0x08]	70	1		T46	1		T43	5		T124	1
valid_sources[0x09]	72	1		T27	4		T69	1		T71	1
valid_sources[0x0a]	72	1		T2	1		T52	1		T48	1
valid_sources[0x0b]	104	1		T125	1		T126	1		T50	17
valid_sources[0x0c]	69	1		T68	1		T50	6		T71	2
valid_sources[0x0d]	67	1		T127	1		T26	4		T32	1
valid_sources[0x0e]	159	1		T19	1		T51	1		T124	1
valid_sources[0x0f]	83	1		T34	4		T128	1		T68	5
valid_sources[0x10]	58	1		T129	1		T32	2		T68	3
valid_sources[0x11]	63	1		T68	5		T71	4		T81	4
valid_sources[0x12]	82	1		T130	1		T131	1		T32	2
valid_sources[0x13]	82	1		T46	1		T60	2		T81	2
valid_sources[0x14]	58	1		T69	2		T60	1		T71	2
valid_sources[0x15]	101	1		T57	13		T126	1		T32	1
valid_sources[0x16]	57	1		T44	1		T68	2		T71	2
valid_sources[0x17]	80	1		T44	1		T127	1		T26	1
valid_sources[0x18]	89	1		T50	21		T69	1		T60	1
valid_sources[0x19]	44	1		T50	3		T71	2		T77	2
valid_sources[0x1a]	67	1		T44	1		T32	1		T28	1
valid_sources[0x1b]	72	1		T27	16		T69	2		T71	1
valid_sources[0x1c]	76	1		T32	1		T50	19		T69	2
valid_sources[0x1d]	170	1		T20	1		T35	2		T50	14
valid_sources[0x1e]	86	1		T47	3		T71	5		T29	3
valid_sources[0x1f]	57	1		T32	1		T68	1		T50	2
valid_sources[0x20]	103	1		T51	1		T27	12		T50	3
valid_sources[0x21]	78	1		T131	2		T28	1		T68	2
valid_sources[0x22]	89	1		T32	1		T27	3		T61	4
valid_sources[0x23]	258	1		T52	1		T123	1		T68	3
valid_sources[0x24]	209	1		T52	1		T27	11		T60	1
valid_sources[0x25]	125	1		T18	1		T130	1		T26	1
valid_sources[0x26]	79	1		T128	1		T130	1		T28	6
valid_sources[0x27]	64	1		T54	1		T71	2		T81	8
valid_sources[0x28]	48	1		T32	1		T73	1		T69	3
valid_sources[0x29]	59	1		T68	4		T69	6		T71	1
valid_sources[0x2a]	83	1		T43	1		T26	5		T69	3
valid_sources[0x2b]	82	1		T27	11		T60	1		T71	1
valid_sources[0x2c]	99	1		T123	1		T132	1		T50	4
valid_sources[0x2d]	69	1		T21	1		T28	10		T69	1
valid_sources[0x2e]	245	1		T54	1		T127	2		T131	1
valid_sources[0x2f]	76	1		T21	1		T67	2		T35	1
valid_sources[0x30]	39	1		T21	1		T52	1		T32	1
valid_sources[0x31]	53	1		T21	1		T68	5		T50	9
valid_sources[0x32]	50	1		T50	3		T60	2		T71	1
valid_sources[0x33]	62	1		T126	1		T130	1		T26	9
valid_sources[0x34]	125	1		T133	1		T129	1		T69	1
valid_sources[0x35]	49	1		T46	1		T32	2		T27	2
valid_sources[0x36]	65	1		T123	1		T46	1		T28	3
valid_sources[0x37]	95	1		T71	3		T81	2		T77	1
valid_sources[0x38]	133	1		T52	2		T128	1		T124	1
valid_sources[0x39]	1034	1		T69	2		T71	1		T81	1
valid_sources[0x3a]	49	1		T35	1		T46	1		T54	1
valid_sources[0x3b]	66	1		T20	1		T21	1		T46	1
valid_sources[0x3c]	69	1		T1	1		T134	10		T28	4
valid_sources[0x3d]	56	1		T32	1		T28	3		T71	1
valid_sources[0x3e]	68	1		T18	1		T32	1		T27	6
valid_sources[0x3f]	62	1		T21	1		T51	2		T28	3
valid_sources[0x40]	92	1		T60	1		T71	4		T81	2
valid_sources[0x41]	42	1		T1	1		T32	2		T71	2
valid_sources[0x42]	55	1		T21	1		T26	7		T71	2
valid_sources[0x43]	97	1		T3	16		T128	1		T69	1
valid_sources[0x44]	150	1		T32	1		T28	3		T50	14
valid_sources[0x45]	67	1		T49	1		T28	2		T68	1
valid_sources[0x46]	157	1		T2	1		T132	1		T32	1
valid_sources[0x47]	52	1		T21	1		T67	2		T60	2
valid_sources[0x48]	61	1		T58	2		T49	1		T69	2
valid_sources[0x49]	66	1		T52	1		T46	1		T27	4
valid_sources[0x4a]	66	1		T28	2		T50	2		T71	2
valid_sources[0x4b]	198	1		T60	1		T71	1		T81	2
valid_sources[0x4c]	62	1		T27	9		T28	3		T68	1
valid_sources[0x4d]	56	1		T133	1		T27	14		T71	2
valid_sources[0x4e]	89	1		T1	1		T44	1		T69	2
valid_sources[0x4f]	110	1		T135	1		T124	1		T32	1
valid_sources[0x50]	112	1		T27	1		T50	3		T60	1
valid_sources[0x51]	111	1		T124	1		T27	1		T28	10
valid_sources[0x52]	68	1		T58	5		T28	1		T50	1
valid_sources[0x53]	69	1		T21	1		T124	1		T28	5
valid_sources[0x54]	92	1		T124	1		T32	1		T27	8
valid_sources[0x55]	68	1		T27	19		T68	2		T69	2
valid_sources[0x56]	66	1		T28	11		T50	2		T69	6
valid_sources[0x57]	63	1		T123	1		T128	1		T27	2
valid_sources[0x58]	51	1		T32	2		T60	1		T81	1
valid_sources[0x59]	159	1		T69	1		T71	5		T77	2
valid_sources[0x5a]	88	1		T2	1		T34	1		T136	1
valid_sources[0x5b]	202	1		T48	5		T128	1		T32	2
valid_sources[0x5c]	82	1		T20	1		T71	5		T81	2
valid_sources[0x5d]	77	1		T50	2		T60	2		T71	1
valid_sources[0x5e]	320	1		T2	1		T69	1		T71	3
valid_sources[0x5f]	71	1		T68	1		T69	1		T71	2
valid_sources[0x60]	113	1		T27	1		T50	7		T71	4
valid_sources[0x61]	80	1		T67	1		T27	7		T50	3
valid_sources[0x62]	193	1		T32	1		T27	9		T69	2
valid_sources[0x63]	105	1		T71	3		T81	1		T77	2
valid_sources[0x64]	144	1		T21	1		T28	3		T68	1
valid_sources[0x65]	51	1		T21	1		T44	1		T32	1
valid_sources[0x66]	63	1		T32	1		T69	1		T60	1
valid_sources[0x67]	78	1		T27	32		T71	1		T83	1
valid_sources[0x68]	51	1		T46	1		T68	2		T50	3
valid_sources[0x69]	54	1		T125	7		T58	3		T43	2
valid_sources[0x6a]	64	1		T71	2		T81	5		T77	8
valid_sources[0x6b]	38	1		T135	1		T128	1		T28	1
valid_sources[0x6c]	57	1		T33	1		T50	6		T73	1
valid_sources[0x6d]	92	1		T1	1		T20	1		T69	9
valid_sources[0x6e]	48	1		T54	1		T137	9		T69	1
valid_sources[0x6f]	247	1		T18	1		T138	12		T32	1
valid_sources[0x70]	71	1		T32	1		T68	1		T50	7
valid_sources[0x71]	60	1		T52	1		T32	1		T50	4
valid_sources[0x72]	39	1		T69	1		T71	3		T81	2
valid_sources[0x73]	45	1		T28	1		T60	2		T71	2
valid_sources[0x74]	273	1		T53	2		T27	1		T68	1
valid_sources[0x75]	77	1		T20	1		T51	1		T139	2
valid_sources[0x76]	56	1		T28	2		T50	9		T69	5
valid_sources[0x77]	72	1		T130	1		T127	1		T69	7
valid_sources[0x78]	94	1		T50	2		T81	4		T30	2
valid_sources[0x79]	205	1		T60	3		T74	9		T71	3
valid_sources[0x7a]	113	1		T124	1		T28	1		T50	10
valid_sources[0x7b]	49	1		T27	9		T69	1		T71	1
valid_sources[0x7c]	141	1		T53	1		T26	1		T68	1
valid_sources[0x7d]	47	1		T20	1		T71	2		T81	1
valid_sources[0x7e]	61	1		T1	2		T27	1		T28	4
valid_sources[0x7f]	145	1		T27	3		T28	3		T69	1
valid_sources[0x80]	98	1		T1	2		T18	1		T71	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6377

1

T26

24

T32

12

T27

131

values[0x0]

all_enables

biggest_size

6781

1

T1

2

T2

1

T3

3

values[0x1]

all_enables

biggest_size

6490

1

T1

1

T3

4

T16

1