SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 796819 | 1 | T5 | 9 | T6 | 43 | T7 | 83 | |||
auto[1] | 16373 | 1 | T14 | 80 | T15 | 80 | T26 | 53 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 812980 | 1 | T5 | 9 | T6 | 43 | T7 | 83 | |||
values[1] | 22 | 1 | T32 | 2 | T30 | 1 | T114 | 1 | |||
values[2] | 5 | 1 | T115 | 2 | T116 | 1 | T111 | 1 | |||
values[3] | 116 | 1 | T32 | 4 | T29 | 4 | T30 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 812970 | 1 | T5 | 9 | T6 | 43 | T7 | 83 | |||
values[1] | 18 | 1 | T30 | 2 | T83 | 3 | T115 | 2 | |||
values[2] | 6 | 1 | T30 | 1 | T83 | 1 | T114 | 1 | |||
values[3] | 115 | 1 | T32 | 4 | T29 | 3 | T30 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 812872 | 1 | T5 | 9 | T6 | 43 | T7 | 83 | |||
auto[TlIntgErrCmd] | 98 | 1 | T32 | 4 | T29 | 4 | T30 | 5 | |||
auto[TlIntgErrData] | 108 | 1 | T32 | 1 | T29 | 4 | T30 | 7 | |||
auto[TlIntgErrBoth] | 114 | 1 | T32 | 5 | T29 | 2 | T30 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 38196 | 0 | T1 | 12 | T2 | 7 | T3 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 37993 | 1 | T1 | 12 | T2 | 7 | T3 | 16 | |||
values[1] | 20 | 1 | T30 | 1 | T117 | 2 | T118 | 2 | |||
values[2] | 6 | 1 | T29 | 2 | T115 | 1 | T62 | 1 | |||
values[3] | 104 | 1 | T32 | 5 | T29 | 5 | T30 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 37980 | 1 | T1 | 12 | T2 | 7 | T3 | 16 | |||
values[1] | 28 | 1 | T29 | 1 | T30 | 1 | T83 | 3 | |||
values[2] | 2 | 1 | T119 | 1 | T120 | 1 | - | - | |||
values[3] | 96 | 1 | T32 | 3 | T29 | 2 | T30 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 37876 | 1 | T1 | 12 | T2 | 7 | T3 | 16 | |||
auto[TlIntgErrCmd] | 104 | 1 | T32 | 3 | T29 | 2 | T30 | 7 | |||
auto[TlIntgErrData] | 117 | 1 | T32 | 3 | T29 | 2 | T30 | 6 | |||
auto[TlIntgErrBoth] | 99 | 1 | T32 | 4 | T29 | 6 | T30 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |