Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	237379	1		T5	3		T6	28		T7	46
full_word	575813	1		T5	6		T6	15		T7	37

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	812872	1		T5	9		T6	43		T7	83
auto[TlIntgErrCmd]	98	1		T32	4		T29	4		T30	5
auto[TlIntgErrData]	108	1		T32	1		T29	4		T30	7
auto[TlIntgErrBoth]	114	1		T32	5		T29	2		T30	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	481125	1		T5	8		T6	12		T7	14
auto[1]	332067	1		T5	1		T6	31		T7	69

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	196295	1		T5	3		T6	9		T7	5
auto[TlIntgErrNone]	partial	auto[1]	40789	1		T6	19		T7	41		T8	1
auto[TlIntgErrNone]	full_word	auto[0]	284692	1		T5	5		T6	3		T7	9
auto[TlIntgErrNone]	full_word	auto[1]	291096	1		T5	1		T6	12		T7	28
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T32	1		T29	1		T30	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T32	3		T29	2		T30	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T29	1		T108	1		T121	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T118	1		T108	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T32	1		T29	2		T30	1
auto[TlIntgErrData]	partial	auto[1]	47	1		T29	1		T30	5		T83	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T29	1		T114	1		T62	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T30	1		T83	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T32	1		T29	1		T30	1
auto[TlIntgErrBoth]	partial	auto[1]	73	1		T32	4		T29	1		T30	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T83	1		T117	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T115	1		T119	1		T62	1