Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 184202 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 502638 1 T4 6 T8 1 T5 35



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 430329 1 T4 6 T5 18 T6 22
values[0x0] 124888 1 T4 6 T8 4 T5 30
values[0x1] 131623 1 T4 2 T8 6 T5 22



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 140061 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 546779 1 T4 6 T8 4 T5 40



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2359 1 T133 1 T134 1 T135 1
valid_sources[0x01] 2423 1 T136 2 T47 15 T48 5
valid_sources[0x02] 2729 1 T137 1 T138 1 T139 1
valid_sources[0x03] 2747 1 T133 2 T47 16 T48 2
valid_sources[0x04] 2668 1 T140 8 T135 1 T47 30
valid_sources[0x05] 2746 1 T40 2 T141 1 T139 1
valid_sources[0x06] 2607 1 T120 2 T18 3 T142 9
valid_sources[0x07] 2707 1 T9 2 T10 1 T18 2
valid_sources[0x08] 2425 1 T137 1 T139 1 T133 4
valid_sources[0x09] 2561 1 T6 3 T9 1 T18 1
valid_sources[0x0a] 2524 1 T143 1 T47 22 T48 2
valid_sources[0x0b] 2877 1 T138 1 T144 8 T145 1
valid_sources[0x0c] 3201 1 T6 2 T135 2 T46 1
valid_sources[0x0d] 2766 1 T10 1 T29 6 T135 1
valid_sources[0x0e] 2534 1 T138 1 T141 1 T139 1
valid_sources[0x0f] 2659 1 T9 1 T146 1 T135 1
valid_sources[0x10] 2519 1 T9 1 T10 2 T141 1
valid_sources[0x11] 3039 1 T10 1 T136 2 T47 19
valid_sources[0x12] 3132 1 T9 1 T32 1 T120 4
valid_sources[0x13] 2614 1 T40 1 T46 9 T47 29
valid_sources[0x14] 2889 1 T141 1 T145 1 T47 23
valid_sources[0x15] 2742 1 T137 1 T146 3 T141 1
valid_sources[0x16] 2673 1 T7 52 T9 1 T10 8
valid_sources[0x17] 2269 1 T6 1 T18 1 T133 1
valid_sources[0x18] 2835 1 T6 2 T9 1 T147 2
valid_sources[0x19] 2942 1 T148 14 T133 1 T46 1
valid_sources[0x1a] 2869 1 T9 2 T137 1 T33 1
valid_sources[0x1b] 3096 1 T28 4 T141 1 T133 1
valid_sources[0x1c] 2640 1 T47 29 T48 1 T59 2
valid_sources[0x1d] 3672 1 T6 2 T10 8 T141 1
valid_sources[0x1e] 2528 1 T42 1 T47 17 T48 4
valid_sources[0x1f] 2448 1 T10 6 T18 1 T139 1
valid_sources[0x20] 2663 1 T141 1 T145 1 T139 1
valid_sources[0x21] 2025 1 T138 1 T133 1 T46 8
valid_sources[0x22] 2400 1 T40 1 T18 4 T138 1
valid_sources[0x23] 2630 1 T40 1 T18 1 T138 1
valid_sources[0x24] 2465 1 T6 1 T9 1 T138 1
valid_sources[0x25] 2847 1 T25 14 T139 2 T149 2
valid_sources[0x26] 3011 1 T9 2 T141 1 T139 1
valid_sources[0x27] 2673 1 T10 6 T18 1 T139 1
valid_sources[0x28] 2717 1 T31 1 T145 1 T46 2
valid_sources[0x29] 2926 1 T18 1 T19 1 T47 22
valid_sources[0x2a] 2393 1 T25 3 T42 1 T137 1
valid_sources[0x2b] 2875 1 T6 1 T145 1 T46 1
valid_sources[0x2c] 2594 1 T25 13 T138 1 T47 17
valid_sources[0x2d] 2572 1 T9 2 T139 1 T133 1
valid_sources[0x2e] 2669 1 T9 1 T137 1 T18 3
valid_sources[0x2f] 3077 1 T137 1 T149 2 T47 11
valid_sources[0x30] 3149 1 T10 1 T18 2 T143 1
valid_sources[0x31] 2793 1 T6 1 T145 1 T136 1
valid_sources[0x32] 2664 1 T9 1 T137 1 T141 1
valid_sources[0x33] 2782 1 T133 3 T135 1 T47 16
valid_sources[0x34] 2868 1 T9 2 T138 2 T133 1
valid_sources[0x35] 2539 1 T9 2 T10 1 T40 1
valid_sources[0x36] 2084 1 T18 2 T150 1 T139 1
valid_sources[0x37] 2476 1 T32 3 T137 1 T138 2
valid_sources[0x38] 2849 1 T6 1 T40 2 T139 1
valid_sources[0x39] 2293 1 T5 70 T42 1 T141 1
valid_sources[0x3a] 2133 1 T9 1 T120 10 T151 1
valid_sources[0x3b] 2532 1 T9 1 T139 1 T136 1
valid_sources[0x3c] 2645 1 T6 2 T9 1 T33 1
valid_sources[0x3d] 3329 1 T150 4 T135 1 T152 1
valid_sources[0x3e] 2581 1 T9 1 T120 1 T133 1
valid_sources[0x3f] 2869 1 T42 1 T47 26 T48 4
valid_sources[0x40] 2421 1 T6 1 T9 1 T120 1
valid_sources[0x41] 2665 1 T6 3 T139 2 T135 1
valid_sources[0x42] 3064 1 T9 1 T32 1 T19 5
valid_sources[0x43] 2995 1 T137 1 T18 1 T143 1
valid_sources[0x44] 2531 1 T9 1 T10 9 T153 81
valid_sources[0x45] 2269 1 T9 1 T40 1 T138 2
valid_sources[0x46] 2525 1 T75 32 T40 1 T150 1
valid_sources[0x47] 2545 1 T40 1 T150 1 T136 1
valid_sources[0x48] 2596 1 T40 1 T145 1 T139 1
valid_sources[0x49] 2882 1 T6 1 T42 1 T150 1
valid_sources[0x4a] 3022 1 T9 1 T32 1 T10 2
valid_sources[0x4b] 2728 1 T10 5 T135 1 T46 3
valid_sources[0x4c] 3000 1 T33 1 T141 2 T46 7
valid_sources[0x4d] 2528 1 T40 4 T139 2 T133 1
valid_sources[0x4e] 2416 1 T9 3 T141 1 T47 26
valid_sources[0x4f] 2475 1 T6 1 T32 1 T19 3
valid_sources[0x50] 2637 1 T152 14 T47 23 T48 5
valid_sources[0x51] 2451 1 T6 1 T9 2 T31 1
valid_sources[0x52] 2287 1 T6 1 T10 4 T120 4
valid_sources[0x53] 2402 1 T9 1 T139 1 T154 5
valid_sources[0x54] 2687 1 T9 1 T10 2 T19 2
valid_sources[0x55] 2593 1 T47 26 T48 5 T76 94
valid_sources[0x56] 3012 1 T25 17 T19 3 T141 1
valid_sources[0x57] 3126 1 T9 1 T10 3 T120 6
valid_sources[0x58] 2341 1 T6 3 T133 2 T154 3
valid_sources[0x59] 2248 1 T139 1 T46 3 T47 17
valid_sources[0x5a] 2397 1 T6 1 T25 6 T40 2
valid_sources[0x5b] 2869 1 T40 1 T136 2 T133 1
valid_sources[0x5c] 2386 1 T120 4 T147 4 T145 1
valid_sources[0x5d] 2649 1 T14 1 T9 2 T10 4
valid_sources[0x5e] 2645 1 T6 3 T9 1 T42 1
valid_sources[0x5f] 2116 1 T25 4 T152 5 T47 18
valid_sources[0x60] 2190 1 T9 1 T10 1 T140 1
valid_sources[0x61] 2029 1 T42 1 T139 1 T46 1
valid_sources[0x62] 2438 1 T9 1 T137 2 T147 3
valid_sources[0x63] 2451 1 T19 7 T145 1 T139 1
valid_sources[0x64] 2339 1 T42 2 T136 3 T133 1
valid_sources[0x65] 4262 1 T145 1 T140 1 T139 1
valid_sources[0x66] 2336 1 T145 1 T140 4 T139 1
valid_sources[0x67] 2948 1 T137 1 T143 1 T145 1
valid_sources[0x68] 3115 1 T42 1 T137 1 T18 1
valid_sources[0x69] 2348 1 T6 2 T155 4 T139 1
valid_sources[0x6a] 2941 1 T9 1 T31 1 T140 2
valid_sources[0x6b] 2220 1 T40 1 T120 1 T139 1
valid_sources[0x6c] 2692 1 T6 3 T40 1 T142 1
valid_sources[0x6d] 2462 1 T6 2 T9 2 T138 1
valid_sources[0x6e] 2634 1 T40 1 T18 9 T139 1
valid_sources[0x6f] 3073 1 T18 2 T47 24 T48 1
valid_sources[0x70] 3263 1 T14 1 T6 6 T138 1
valid_sources[0x71] 2157 1 T6 1 T9 2 T120 9
valid_sources[0x72] 2300 1 T40 1 T42 1 T133 1
valid_sources[0x73] 2767 1 T18 3 T138 1 T135 1
valid_sources[0x74] 2717 1 T120 9 T142 1 T155 3
valid_sources[0x75] 2666 1 T136 2 T133 1 T47 15
valid_sources[0x76] 2960 1 T9 1 T40 1 T139 2
valid_sources[0x77] 3005 1 T9 2 T42 1 T142 2
valid_sources[0x78] 4097 1 T6 1 T137 1 T133 1
valid_sources[0x79] 2697 1 T8 3 T6 3 T139 1
valid_sources[0x7a] 2479 1 T140 2 T47 19 T59 5
valid_sources[0x7b] 3036 1 T137 1 T145 1 T47 17
valid_sources[0x7c] 3088 1 T40 1 T135 1 T46 13
valid_sources[0x7d] 3039 1 T142 2 T47 20 T48 1
valid_sources[0x7e] 2358 1 T6 1 T135 1 T152 8
valid_sources[0x7f] 2481 1 T146 1 T141 1 T145 1
valid_sources[0x80] 3102 1 T10 1 T120 13 T145 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 257909 1 T4 3 T5 6 T6 16
values[0x0] all_enables biggest_size 122571 1 T4 2 T8 1 T5 17
values[0x1] all_enables biggest_size 122158 1 T4 1 T5 12 T6 14


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3968 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21796 1 T3 4 T35 2 T36 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8991 1 T46 7 T47 33 T48 90
values[0x0] 8140 1 T3 10 T35 9 T36 2
values[0x1] 8633 1 T3 11 T35 4 T36 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2940 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 22824 1 T3 6 T35 2 T36 6



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 72 1 T66 1 T59 1 T70 2
valid_sources[0x01] 67 1 T156 1 T59 1 T68 1
valid_sources[0x02] 132 1 T68 1 T78 3 T70 2
valid_sources[0x03] 53 1 T59 1 T68 3 T78 1
valid_sources[0x04] 73 1 T3 4 T115 1 T69 1
valid_sources[0x05] 105 1 T49 1 T59 1 T70 4
valid_sources[0x06] 65 1 T68 1 T69 1 T77 2
valid_sources[0x07] 195 1 T68 4 T78 5 T70 2
valid_sources[0x08] 116 1 T157 6 T54 1 T73 4
valid_sources[0x09] 75 1 T158 8 T59 2 T70 2
valid_sources[0x0a] 59 1 T77 2 T78 1 T70 1
valid_sources[0x0b] 100 1 T159 1 T68 2 T61 25
valid_sources[0x0c] 104 1 T115 1 T160 1 T68 3
valid_sources[0x0d] 162 1 T78 1 T70 2 T54 9
valid_sources[0x0e] 70 1 T3 1 T161 1 T59 2
valid_sources[0x0f] 52 1 T68 3 T78 2 T54 1
valid_sources[0x10] 70 1 T162 2 T59 1 T68 7
valid_sources[0x11] 81 1 T49 1 T68 2 T78 3
valid_sources[0x12] 56 1 T163 1 T68 1 T78 1
valid_sources[0x13] 98 1 T164 1 T59 1 T69 1
valid_sources[0x14] 98 1 T115 1 T68 1 T78 3
valid_sources[0x15] 111 1 T3 2 T67 9 T74 1
valid_sources[0x16] 70 1 T68 1 T78 2 T54 14
valid_sources[0x17] 248 1 T74 1 T76 155 T68 1
valid_sources[0x18] 131 1 T78 1 T54 9 T165 1
valid_sources[0x19] 89 1 T47 15 T59 2 T69 1
valid_sources[0x1a] 135 1 T47 10 T68 3 T61 1
valid_sources[0x1b] 83 1 T47 2 T68 2 T78 3
valid_sources[0x1c] 73 1 T68 4 T78 9 T70 1
valid_sources[0x1d] 65 1 T166 2 T61 5 T78 1
valid_sources[0x1e] 89 1 T35 1 T46 1 T59 1
valid_sources[0x1f] 256 1 T47 3 T48 104 T68 4
valid_sources[0x20] 83 1 T167 4 T68 3 T78 1
valid_sources[0x21] 70 1 T168 1 T47 3 T59 2
valid_sources[0x22] 87 1 T159 3 T78 3 T54 5
valid_sources[0x23] 81 1 T169 1 T69 1 T78 4
valid_sources[0x24] 115 1 T68 3 T78 1 T54 7
valid_sources[0x25] 110 1 T166 2 T47 4 T59 1
valid_sources[0x26] 107 1 T59 3 T54 8 T73 6
valid_sources[0x27] 82 1 T68 5 T78 2 T70 1
valid_sources[0x28] 57 1 T47 2 T70 5 T54 6
valid_sources[0x29] 67 1 T160 1 T170 1 T68 3
valid_sources[0x2a] 62 1 T69 1 T78 3 T70 2
valid_sources[0x2b] 80 1 T46 1 T68 6 T78 1
valid_sources[0x2c] 99 1 T3 1 T70 1 T54 3
valid_sources[0x2d] 105 1 T160 3 T68 2 T78 3
valid_sources[0x2e] 117 1 T156 3 T46 3 T68 2
valid_sources[0x2f] 98 1 T70 2 T71 11 T54 16
valid_sources[0x30] 169 1 T65 2 T171 2 T78 2
valid_sources[0x31] 77 1 T70 2 T54 7 T72 1
valid_sources[0x32] 74 1 T59 3 T68 5 T70 1
valid_sources[0x33] 74 1 T64 1 T59 1 T68 4
valid_sources[0x34] 94 1 T68 2 T78 3 T70 6
valid_sources[0x35] 70 1 T68 4 T78 1 T79 1
valid_sources[0x36] 86 1 T168 1 T161 1 T46 1
valid_sources[0x37] 171 1 T59 1 T68 3 T78 4
valid_sources[0x38] 87 1 T70 6 T54 13 T73 3
valid_sources[0x39] 83 1 T59 1 T68 1 T78 1
valid_sources[0x3a] 48 1 T46 1 T68 2 T78 3
valid_sources[0x3b] 138 1 T161 2 T68 2 T61 3
valid_sources[0x3c] 86 1 T68 3 T78 1 T70 1
valid_sources[0x3d] 173 1 T59 1 T76 101 T78 4
valid_sources[0x3e] 157 1 T49 2 T172 6 T68 6
valid_sources[0x3f] 89 1 T35 2 T46 1 T68 1
valid_sources[0x40] 110 1 T54 29 T83 4 T165 2
valid_sources[0x41] 56 1 T66 1 T115 1 T68 2
valid_sources[0x42] 103 1 T173 5 T60 14 T71 6
valid_sources[0x43] 70 1 T78 4 T83 2 T165 3
valid_sources[0x44] 119 1 T48 54 T68 1 T54 2
valid_sources[0x45] 87 1 T59 1 T68 2 T78 1
valid_sources[0x46] 96 1 T170 1 T47 7 T68 2
valid_sources[0x47] 56 1 T78 2 T70 1 T83 4
valid_sources[0x48] 130 1 T70 2 T54 10 T82 2
valid_sources[0x49] 79 1 T68 3 T69 1 T78 1
valid_sources[0x4a] 113 1 T115 1 T59 1 T68 2
valid_sources[0x4b] 59 1 T68 3 T83 6 T132 3
valid_sources[0x4c] 468 1 T59 2 T71 5 T73 2
valid_sources[0x4d] 127 1 T115 1 T168 1 T78 4
valid_sources[0x4e] 82 1 T68 1 T61 2 T78 2
valid_sources[0x4f] 138 1 T162 1 T48 35 T69 2
valid_sources[0x50] 189 1 T78 1 T70 7 T83 3
valid_sources[0x51] 88 1 T78 7 T70 3 T54 2
valid_sources[0x52] 73 1 T68 4 T78 2 T70 2
valid_sources[0x53] 137 1 T169 1 T48 4 T68 8
valid_sources[0x54] 134 1 T115 1 T174 6 T78 3
valid_sources[0x55] 102 1 T66 1 T173 3 T77 2
valid_sources[0x56] 74 1 T68 2 T54 6 T81 1
valid_sources[0x57] 91 1 T170 2 T59 1 T78 1
valid_sources[0x58] 107 1 T35 1 T114 2 T68 2
valid_sources[0x59] 83 1 T115 1 T83 5 T165 4
valid_sources[0x5a] 96 1 T43 1 T115 1 T175 2
valid_sources[0x5b] 61 1 T68 1 T72 1 T165 1
valid_sources[0x5c] 104 1 T68 1 T78 1 T54 10
valid_sources[0x5d] 123 1 T176 1 T68 2 T69 1
valid_sources[0x5e] 79 1 T162 1 T170 1 T59 1
valid_sources[0x5f] 94 1 T48 35 T78 1 T70 3
valid_sources[0x60] 72 1 T169 1 T68 3 T54 10
valid_sources[0x61] 78 1 T68 1 T78 6 T70 1
valid_sources[0x62] 98 1 T59 1 T68 3 T70 5
valid_sources[0x63] 88 1 T68 1 T54 16 T83 3
valid_sources[0x64] 53 1 T177 2 T59 1 T68 1
valid_sources[0x65] 83 1 T61 7 T69 1 T78 6
valid_sources[0x66] 97 1 T64 2 T59 2 T83 1
valid_sources[0x67] 104 1 T68 2 T70 1 T54 11
valid_sources[0x68] 113 1 T49 1 T176 1 T68 1
valid_sources[0x69] 75 1 T59 2 T69 2 T78 3
valid_sources[0x6a] 124 1 T68 1 T78 1 T70 1
valid_sources[0x6b] 225 1 T78 1 T70 3 T83 4
valid_sources[0x6c] 94 1 T163 1 T68 2 T54 3
valid_sources[0x6d] 74 1 T68 1 T78 3 T54 4
valid_sources[0x6e] 73 1 T163 1 T68 6 T70 1
valid_sources[0x6f] 120 1 T70 1 T73 4 T165 1
valid_sources[0x70] 83 1 T171 1 T48 1 T59 2
valid_sources[0x71] 71 1 T156 1 T68 2 T70 3
valid_sources[0x72] 95 1 T59 1 T68 4 T78 1
valid_sources[0x73] 79 1 T70 3 T54 14 T116 1
valid_sources[0x74] 133 1 T163 4 T68 1 T78 1
valid_sources[0x75] 83 1 T64 1 T47 6 T59 1
valid_sources[0x76] 107 1 T178 8 T179 1 T46 2
valid_sources[0x77] 67 1 T168 1 T78 2 T54 10
valid_sources[0x78] 108 1 T122 6 T180 9 T48 1
valid_sources[0x79] 81 1 T3 6 T59 1 T69 1
valid_sources[0x7a] 133 1 T66 2 T68 1 T78 5
valid_sources[0x7b] 68 1 T168 2 T68 1 T69 2
valid_sources[0x7c] 259 1 T181 7 T182 13 T68 3
valid_sources[0x7d] 99 1 T68 1 T78 4 T70 5
valid_sources[0x7e] 235 1 T60 135 T78 1 T70 3
valid_sources[0x7f] 69 1 T35 1 T78 3 T54 2
valid_sources[0x80] 56 1 T61 4 T77 1 T78 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6822 1 T46 2 T47 14 T48 83
values[0x0] all_enables biggest_size 7459 1 T3 2 T35 2 T36 1
values[0x1] all_enables biggest_size 7515 1 T3 2 T36 1 T49 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%