Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	238353	1		T4	8		T8	9		T5	35
full_word	504725	1		T4	6		T8	1		T5	35

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	742818	1		T4	14		T8	10		T5	70
auto[TlIntgErrCmd]	85	1		T47	1		T69	2		T71	10
auto[TlIntgErrData]	81	1		T47	5		T69	3		T71	4
auto[TlIntgErrBoth]	94	1		T47	4		T69	5		T71	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	432807	1		T4	6		T5	18		T6	22
auto[1]	310271	1		T4	8		T8	10		T5	52

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	174541	1		T4	3		T5	12		T6	6
auto[TlIntgErrNone]	partial	auto[1]	63569	1		T4	5		T8	9		T5	23
auto[TlIntgErrNone]	full_word	auto[0]	258143	1		T4	3		T5	6		T6	16
auto[TlIntgErrNone]	full_word	auto[1]	246565	1		T4	3		T8	1		T5	29
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T47	1		T69	1		T71	7
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T69	1		T71	3		T124	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T129	1		T126	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T131	2		T125	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1		T47	2		T69	1		T71	4
auto[TlIntgErrData]	partial	auto[1]	36	1		T47	2		T69	1		T124	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T47	1		T69	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T127	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T47	2		T69	1		T71	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T47	2		T69	3		T71	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T71	1		T130	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T69	1		T71	1		T124	1