SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.71 | 100.00 | 55.32 | 85.71 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 236189738 | 18005 | 0 | 0 |
late_debug_enable_rd_A | 236189738 | 5173 | 0 | 0 |
late_debug_enable_regwen_rd_A | 236189738 | 4186 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 236189738 | 18005 | 0 | 0 |
T46 | 10127 | 8 | 0 | 0 |
T47 | 68997 | 1 | 0 | 0 |
T48 | 881112 | 237 | 0 | 0 |
T59 | 265921 | 44 | 0 | 0 |
T60 | 23220 | 769 | 0 | 0 |
T61 | 14025 | 204 | 0 | 0 |
T68 | 33772 | 129 | 0 | 0 |
T69 | 59283 | 1 | 0 | 0 |
T70 | 35220 | 295 | 0 | 0 |
T71 | 200336 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 236189738 | 5173 | 0 | 0 |
T48 | 881112 | 112 | 0 | 0 |
T54 | 184221 | 259 | 0 | 0 |
T61 | 14025 | 49 | 0 | 0 |
T70 | 35220 | 100 | 0 | 0 |
T73 | 26181 | 104 | 0 | 0 |
T76 | 458344 | 971 | 0 | 0 |
T83 | 214135 | 961 | 0 | 0 |
T116 | 11097 | 27 | 0 | 0 |
T117 | 256656 | 59 | 0 | 0 |
T118 | 22539 | 129 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 236189738 | 4186 | 0 | 0 |
T48 | 881112 | 95 | 0 | 0 |
T54 | 184221 | 300 | 0 | 0 |
T61 | 14025 | 18 | 0 | 0 |
T70 | 35220 | 75 | 0 | 0 |
T73 | 26181 | 139 | 0 | 0 |
T83 | 214135 | 1061 | 0 | 0 |
T116 | 11097 | 28 | 0 | 0 |
T117 | 256656 | 31 | 0 | 0 |
T118 | 22539 | 138 | 0 | 0 |
T119 | 9480 | 42 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |