Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.71	100.00	55.32	85.71		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	236189738	18005	0	0
late_debug_enable_rd_A	236189738	5173	0	0
late_debug_enable_regwen_rd_A	236189738	4186	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236189738	18005	0	0
T46	10127	8	0	0
T47	68997	1	0	0
T48	881112	237	0	0
T59	265921	44	0	0
T60	23220	769	0	0
T61	14025	204	0	0
T68	33772	129	0	0
T69	59283	1	0	0
T70	35220	295	0	0
T71	200336	8	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236189738	5173	0	0
T48	881112	112	0	0
T54	184221	259	0	0
T61	14025	49	0	0
T70	35220	100	0	0
T73	26181	104	0	0
T76	458344	971	0	0
T83	214135	961	0	0
T116	11097	27	0	0
T117	256656	59	0	0
T118	22539	129	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236189738	4186	0	0
T48	881112	95	0	0
T54	184221	300	0	0
T61	14025	18	0	0
T70	35220	75	0	0
T73	26181	139	0	0
T83	214135	1061	0	0
T116	11097	28	0	0
T117	256656	31	0	0
T118	22539	138	0	0
T119	9480	42	0	0