Line Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 4 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
1 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Cond Coverage for Module :
tlul_adapter_host
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T2,T11,T12 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T2,T11,T12 |
1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T2,T11,T12 |
1 | Covered | T2,T11,T12 |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T11,T12,T13 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T11,T12,T13 |
1 | 0 | Covered | T11,T12,T13 |
Branch Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
94 |
2 |
2 |
100.00 |
IF |
132 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T11,T12 |
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T11,T12,T13 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_host
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236189738 |
49570 |
0 |
0 |
T2 |
148629 |
469 |
0 |
0 |
T3 |
3913 |
0 |
0 |
0 |
T4 |
635718 |
0 |
0 |
0 |
T5 |
297114 |
0 |
0 |
0 |
T8 |
68955 |
0 |
0 |
0 |
T11 |
785239 |
63 |
0 |
0 |
T12 |
203593 |
870 |
0 |
0 |
T13 |
314024 |
155 |
0 |
0 |
T20 |
137404 |
386 |
0 |
0 |
T21 |
680142 |
906 |
0 |
0 |
T44 |
0 |
439 |
0 |
0 |
T50 |
0 |
1070 |
0 |
0 |
T53 |
0 |
177 |
0 |
0 |
T86 |
0 |
993 |
0 |
0 |