Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm_regs_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.19 98.69 98.71 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.71 100.00 55.32 85.71 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_chk 97.78 100.00 93.33 100.00
u_late_debug_enable 100.00 100.00 100.00 100.00
u_late_debug_enable_regwen 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm_regs_reg_top
Line No.TotalCoveredPercent
TOTAL3535100.00
ALWAYS6744100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN18411100.00
ALWAYS21544100.00
CONT_ASSIGN22111100.00
ALWAYS22511100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24011100.00
ALWAYS24444100.00
ALWAYS25255100.00
CONT_ASSIGN27700
CONT_ASSIGN28511100.00
CONT_ASSIGN28611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
67 1 1
68 1 1
69 1 1
70 1 1
MISSING_ELSE
76 1 1
88 1 1
89 1 1
117 1 1
118 1 1
136 1 1
150 1 1
184 1 1
215 1 1
216 1 1
217 1 1
218 1 1
221 1 1
225 1 1
232 1 1
234 1 1
235 1 1
237 1 1
238 1 1
240 1 1
244 1 1
245 1 1
246 1 1
247 1 1
252 1 1
253 1 1
255 1 1
259 1 1
263 1 1
277 unreachable
285 1 1
286 1 1


Cond Coverage for Module : rv_dm_regs_reg_top
TotalCoveredPercent
Conditions5656100.00
Logical5656100.00
Non-Logical00
Event00

 LINE       57
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT46,T48,T59
11CoveredT3,T35,T36

 LINE       69
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT37,T38,T39
10CoveredT47,T69,T71

 LINE       76
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT37,T38,T39
010CoveredT47,T69,T71
100CoveredT37,T38,T39

 LINE       118
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT47,T69,T71
010CoveredT48,T59,T60
100CoveredT46,T48,T59

 LINE       184
 EXPRESSION (late_debug_enable_we & late_debug_enable_regwen_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT46,T47,T76
11CoveredT47,T59,T68

 LINE       216
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT3,T20,T35
1CoveredT3,T35,T36

 LINE       217
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_REGWEN_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT3,T20,T35
1CoveredT36,T45,T39

 LINE       218
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT3,T35,T36
1CoveredT20,T36,T39

 LINE       221
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T35,T36

 LINE       221
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T35,T36
10CoveredT46,T47,T48

 LINE       225
 EXPRESSION (reg_we & ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))))
             ---1--   ----------------------------------------------------------------2---------------------------------------------------------------
-1--2-StatusTests
01CoveredT20,T44,T36
10CoveredT3,T35,T36
11CoveredT47,T48,T59

 LINE       225
 SUB-EXPRESSION ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))))
                 -------------------1-------------------   -------------------2-------------------   ---------------------3--------------------
-1--2--3-StatusTests
000CoveredT3,T35,T36
001CoveredT20,T44,T36
010CoveredT36,T45,T39
100CoveredT39,T43,T114

 LINE       225
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT20,T44,T36
10CoveredT3,T35,T36
11CoveredT39,T43,T114

 LINE       225
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT20,T44,T36
10CoveredT36,T39,T121
11CoveredT36,T45,T39

 LINE       225
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT3,T35,T36
10CoveredT36,T115,T122
11CoveredT20,T44,T36

 LINE       232
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT46,T47,T59
101CoveredT3,T35,T36
110CoveredT47,T48,T59
111CoveredT3,T35,T36

 LINE       235
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT3,T35,T36
101CoveredT36,T45,T39
110CoveredT48,T59,T69
111CoveredT46,T47,T59

 LINE       238
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT3,T35,T36
101CoveredT20,T44,T36
110CoveredT47,T48,T59
111CoveredT46,T47,T59

Branch Coverage for Module : rv_dm_regs_reg_top
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 221 2 2 100.00
IF 67 3 3 100.00
CASE 253 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 221 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T3,T35,T36
0 Covered T1,T2,T3


LineNo. Expression -1-: 67 if ((!rst_ni)) -2-: 69 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T37,T38,T39
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 253 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : rv_dm_regs_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 236189738 7766 0 0
reAfterRv 236189738 7766 0 0
rePulse 236189738 4394 0 0
wePulse 236189738 3372 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 236189738 7766 0 0
T3 3913 21 0 0
T4 635718 0 0 0
T5 297114 0 0 0
T8 68955 0 0 0
T11 785239 0 0 0
T12 203593 0 0 0
T13 314024 0 0 0
T14 17851 0 0 0
T20 137404 0 0 0
T21 680142 0 0 0
T35 0 13 0 0
T36 0 7 0 0
T43 0 8 0 0
T49 0 11 0 0
T58 0 1 0 0
T64 0 9 0 0
T65 0 9 0 0
T66 0 7 0 0
T67 0 9 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 236189738 7766 0 0
T3 3913 21 0 0
T4 635718 0 0 0
T5 297114 0 0 0
T8 68955 0 0 0
T11 785239 0 0 0
T12 203593 0 0 0
T13 314024 0 0 0
T14 17851 0 0 0
T20 137404 0 0 0
T21 680142 0 0 0
T35 0 13 0 0
T36 0 7 0 0
T43 0 8 0 0
T49 0 11 0 0
T58 0 1 0 0
T64 0 9 0 0
T65 0 9 0 0
T66 0 7 0 0
T67 0 9 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 236189738 4394 0 0
T46 10127 6 0 0
T47 68997 33 0 0
T48 881112 8 0 0
T59 265921 6 0 0
T60 23220 9 0 0
T61 14025 3 0 0
T68 33772 6 0 0
T69 59283 35 0 0
T76 458344 568 0 0
T77 7002 11 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 236189738 3372 0 0
T3 3913 21 0 0
T4 635718 0 0 0
T5 297114 0 0 0
T8 68955 0 0 0
T11 785239 0 0 0
T12 203593 0 0 0
T13 314024 0 0 0
T14 17851 0 0 0
T20 137404 0 0 0
T21 680142 0 0 0
T35 0 13 0 0
T36 0 7 0 0
T43 0 8 0 0
T49 0 11 0 0
T58 0 1 0 0
T64 0 9 0 0
T65 0 9 0 0
T66 0 7 0 0
T67 0 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%