Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	235957	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	613339	1		T11	80		T9	4		T6	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	541098	1		T11	80		T9	8		T7	6
values[0x0]	150089	1		T9	1		T10	1		T6	8
values[0x1]	158109	1		T10	1		T6	12		T7	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	178038	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	671258	1		T11	80		T9	5		T6	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3793	1		T6	1		T140	26		T141	1
valid_sources[0x01]	3778	1		T11	2		T25	1		T142	1
valid_sources[0x02]	3222	1		T14	1		T143	6		T62	3
valid_sources[0x03]	3722	1		T7	1		T23	1		T62	2
valid_sources[0x04]	3260	1		T144	2		T62	1		T56	2
valid_sources[0x05]	3124	1		T17	4		T14	3		T62	6
valid_sources[0x06]	3763	1		T145	1		T62	2		T56	1
valid_sources[0x07]	3449	1		T146	2		T147	1		T145	1
valid_sources[0x08]	3117	1		T11	2		T25	1		T148	1
valid_sources[0x09]	3016	1		T11	2		T147	1		T62	6
valid_sources[0x0a]	3217	1		T11	2		T14	3		T141	2
valid_sources[0x0b]	3404	1		T25	3		T62	1		T56	2
valid_sources[0x0c]	3598	1		T8	1		T62	1		T56	1
valid_sources[0x0d]	3581	1		T11	2		T7	1		T14	2
valid_sources[0x0e]	2918	1		T8	1		T25	2		T17	2
valid_sources[0x0f]	3677	1		T7	1		T147	1		T149	5
valid_sources[0x10]	3294	1		T23	5		T148	1		T56	4
valid_sources[0x11]	3376	1		T8	1		T25	1		T141	1
valid_sources[0x12]	3275	1		T62	1		T56	3		T57	3
valid_sources[0x13]	2855	1		T62	2		T56	3		T57	5
valid_sources[0x14]	3419	1		T14	1		T150	6		T141	1
valid_sources[0x15]	3469	1		T14	1		T62	2		T56	2
valid_sources[0x16]	3690	1		T23	1		T145	1		T141	1
valid_sources[0x17]	2976	1		T11	1		T6	1		T25	1
valid_sources[0x18]	3044	1		T8	3		T62	2		T57	7
valid_sources[0x19]	2884	1		T7	1		T14	1		T148	2
valid_sources[0x1a]	3753	1		T7	1		T23	1		T150	4
valid_sources[0x1b]	3612	1		T69	1		T14	1		T62	2
valid_sources[0x1c]	3292	1		T62	2		T57	3		T58	5
valid_sources[0x1d]	2941	1		T11	3		T7	2		T145	1
valid_sources[0x1e]	3791	1		T25	1		T14	1		T23	2
valid_sources[0x1f]	3452	1		T9	1		T7	2		T62	1
valid_sources[0x20]	3395	1		T144	1		T62	1		T56	2
valid_sources[0x21]	3118	1		T8	2		T141	1		T62	3
valid_sources[0x22]	3141	1		T148	1		T62	2		T56	2
valid_sources[0x23]	3771	1		T144	1		T141	1		T62	2
valid_sources[0x24]	2932	1		T150	2		T56	2		T57	1
valid_sources[0x25]	3325	1		T11	1		T9	2		T25	1
valid_sources[0x26]	3181	1		T7	1		T62	1		T56	2
valid_sources[0x27]	3133	1		T7	2		T143	13		T62	5
valid_sources[0x28]	3851	1		T11	5		T8	2		T14	1
valid_sources[0x29]	2958	1		T11	2		T8	1		T147	1
valid_sources[0x2a]	3636	1		T7	1		T25	1		T15	98
valid_sources[0x2b]	3284	1		T145	1		T62	2		T56	5
valid_sources[0x2c]	3391	1		T34	59		T62	4		T56	1
valid_sources[0x2d]	3442	1		T147	1		T62	1		T56	2
valid_sources[0x2e]	3101	1		T62	2		T57	3		T58	4
valid_sources[0x2f]	3364	1		T14	1		T62	2		T56	1
valid_sources[0x30]	3330	1		T141	1		T62	1		T56	1
valid_sources[0x31]	3373	1		T145	1		T62	4		T56	2
valid_sources[0x32]	3574	1		T23	3		T150	2		T62	2
valid_sources[0x33]	3532	1		T14	1		T144	1		T148	1
valid_sources[0x34]	3464	1		T25	2		T144	1		T62	2
valid_sources[0x35]	2968	1		T11	2		T150	7		T62	1
valid_sources[0x36]	3530	1		T14	1		T148	1		T141	2
valid_sources[0x37]	3658	1		T7	1		T25	2		T145	2
valid_sources[0x38]	2916	1		T145	1		T62	1		T56	3
valid_sources[0x39]	3863	1		T11	1		T16	1		T62	3
valid_sources[0x3a]	3211	1		T14	1		T145	3		T62	1
valid_sources[0x3b]	3780	1		T7	1		T14	2		T141	1
valid_sources[0x3c]	3483	1		T6	3		T69	1		T56	1
valid_sources[0x3d]	2793	1		T144	1		T145	1		T148	2
valid_sources[0x3e]	3216	1		T62	2		T56	4		T57	1
valid_sources[0x3f]	4172	1		T6	1		T62	5		T56	1
valid_sources[0x40]	3341	1		T8	1		T150	1		T141	2
valid_sources[0x41]	3563	1		T62	5		T56	7		T57	4
valid_sources[0x42]	2860	1		T23	1		T149	1		T62	5
valid_sources[0x43]	3667	1		T62	3		T57	6		T58	3
valid_sources[0x44]	2980	1		T7	1		T62	2		T56	1
valid_sources[0x45]	3704	1		T8	1		T16	3		T145	1
valid_sources[0x46]	3199	1		T25	1		T62	1		T56	1
valid_sources[0x47]	3377	1		T8	3		T37	1		T23	1
valid_sources[0x48]	2986	1		T25	3		T62	4		T56	2
valid_sources[0x49]	4069	1		T8	2		T69	1		T62	3
valid_sources[0x4a]	3200	1		T62	3		T56	2		T57	4
valid_sources[0x4b]	3184	1		T14	3		T23	1		T62	4
valid_sources[0x4c]	3396	1		T23	1		T62	2		T56	1
valid_sources[0x4d]	3559	1		T11	1		T62	4		T56	1
valid_sources[0x4e]	2921	1		T7	1		T20	1		T14	1
valid_sources[0x4f]	3588	1		T11	1		T7	1		T148	1
valid_sources[0x50]	3334	1		T21	28		T149	1		T151	2
valid_sources[0x51]	3169	1		T11	2		T7	2		T14	1
valid_sources[0x52]	3309	1		T11	2		T6	1		T7	1
valid_sources[0x53]	3527	1		T8	4		T148	2		T141	1
valid_sources[0x54]	3186	1		T11	1		T7	1		T25	1
valid_sources[0x55]	3371	1		T7	1		T62	4		T56	2
valid_sources[0x56]	3143	1		T149	1		T62	2		T56	1
valid_sources[0x57]	3116	1		T147	1		T145	1		T62	2
valid_sources[0x58]	4444	1		T9	1		T7	2		T62	2
valid_sources[0x59]	3195	1		T7	1		T150	6		T62	1
valid_sources[0x5a]	3543	1		T62	1		T56	1		T57	3
valid_sources[0x5b]	2953	1		T7	1		T8	2		T57	1
valid_sources[0x5c]	3555	1		T147	1		T148	2		T62	1
valid_sources[0x5d]	2824	1		T23	1		T147	1		T57	4
valid_sources[0x5e]	3279	1		T14	1		T62	2		T56	5
valid_sources[0x5f]	2914	1		T150	3		T56	2		T57	6
valid_sources[0x60]	3461	1		T25	3		T69	1		T152	14
valid_sources[0x61]	3340	1		T7	1		T8	2		T62	2
valid_sources[0x62]	3100	1		T16	1		T62	4		T56	2
valid_sources[0x63]	3447	1		T11	1		T62	3		T56	1
valid_sources[0x64]	3305	1		T141	2		T62	1		T56	4
valid_sources[0x65]	3869	1		T11	3		T6	1		T7	1
valid_sources[0x66]	3330	1		T39	3		T62	5		T56	3
valid_sources[0x67]	3836	1		T62	5		T56	1		T57	11
valid_sources[0x68]	3177	1		T8	1		T141	2		T62	1
valid_sources[0x69]	3089	1		T25	1		T62	4		T57	4
valid_sources[0x6a]	4276	1		T14	1		T62	2		T56	1
valid_sources[0x6b]	3030	1		T33	28		T62	2		T56	3
valid_sources[0x6c]	3118	1		T25	2		T63	14		T146	2
valid_sources[0x6d]	3303	1		T145	1		T62	1		T56	1
valid_sources[0x6e]	3041	1		T62	2		T56	3		T57	2
valid_sources[0x6f]	3565	1		T145	1		T148	1		T141	1
valid_sources[0x70]	3537	1		T62	3		T56	1		T57	1
valid_sources[0x71]	3894	1		T7	1		T141	1		T62	2
valid_sources[0x72]	3061	1		T11	1		T25	1		T56	1
valid_sources[0x73]	3583	1		T7	1		T14	2		T145	1
valid_sources[0x74]	3776	1		T145	1		T62	2		T56	4
valid_sources[0x75]	2973	1		T38	11		T62	2		T56	3
valid_sources[0x76]	2908	1		T144	1		T150	3		T57	4
valid_sources[0x77]	3060	1		T6	2		T25	1		T62	2
valid_sources[0x78]	2960	1		T37	1		T141	1		T62	2
valid_sources[0x79]	2827	1		T7	1		T16	1		T62	2
valid_sources[0x7a]	3442	1		T11	1		T6	2		T25	1
valid_sources[0x7b]	3235	1		T7	1		T148	1		T62	1
valid_sources[0x7c]	3505	1		T62	2		T56	2		T57	1
valid_sources[0x7d]	3412	1		T23	2		T145	2		T141	1
valid_sources[0x7e]	3708	1		T11	1		T141	1		T62	4
valid_sources[0x7f]	3517	1		T8	6		T25	1		T141	4
valid_sources[0x80]	3081	1		T10	1		T8	1		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

318047

1

T11

80

T9

4

T7

3

values[0x0]

all_enables

biggest_size

147715

1

T6

2

T7

11

T8

8

values[0x1]

all_enables

biggest_size

147577

1

T6

3

T7

6

T8

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5287	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	28955	1		T30	1		T47	1		T48	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12255	1		T62	3		T56	170		T57	165
values[0x0]	10771	1		T3	1		T27	1		T28	1
values[0x1]	11216	1		T30	2		T47	3		T48	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3945	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	30297	1		T30	2		T47	2		T48	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	78	1		T153	1		T57	2		T58	2
valid_sources[0x01]	120	1		T57	2		T58	2		T79	2
valid_sources[0x02]	112	1		T154	15		T57	3		T58	2
valid_sources[0x03]	91	1		T155	1		T57	3		T58	2
valid_sources[0x04]	112	1		T68	1		T57	5		T58	5
valid_sources[0x05]	121	1		T57	7		T58	3		T54	3
valid_sources[0x06]	109	1		T57	2		T58	1		T79	3
valid_sources[0x07]	152	1		T156	1		T57	5		T58	2
valid_sources[0x08]	119	1		T52	1		T57	2		T58	3
valid_sources[0x09]	119	1		T89	2		T80	1		T94	4
valid_sources[0x0a]	98	1		T57	1		T58	1		T79	3
valid_sources[0x0b]	166	1		T56	8		T57	2		T58	2
valid_sources[0x0c]	125	1		T124	1		T57	1		T79	3
valid_sources[0x0d]	89	1		T157	1		T57	3		T55	1
valid_sources[0x0e]	113	1		T125	2		T57	2		T54	1
valid_sources[0x0f]	553	1		T57	2		T79	1		T89	2
valid_sources[0x10]	90	1		T87	1		T58	1		T79	3
valid_sources[0x11]	124	1		T56	5		T57	3		T58	3
valid_sources[0x12]	130	1		T87	1		T57	1		T89	5
valid_sources[0x13]	96	1		T57	4		T58	7		T55	1
valid_sources[0x14]	157	1		T61	1		T57	5		T58	1
valid_sources[0x15]	147	1		T52	1		T57	3		T58	3
valid_sources[0x16]	106	1		T47	1		T158	1		T56	7
valid_sources[0x17]	163	1		T57	4		T58	1		T79	1
valid_sources[0x18]	116	1		T61	1		T77	1		T159	1
valid_sources[0x19]	114	1		T58	2		T79	1		T89	3
valid_sources[0x1a]	120	1		T58	3		T54	3		T79	2
valid_sources[0x1b]	97	1		T160	1		T57	2		T79	3
valid_sources[0x1c]	63	1		T159	1		T57	2		T58	3
valid_sources[0x1d]	200	1		T57	3		T58	1		T55	3
valid_sources[0x1e]	79	1		T161	1		T57	1		T58	3
valid_sources[0x1f]	100	1		T57	3		T58	1		T79	1
valid_sources[0x20]	127	1		T87	1		T57	2		T58	3
valid_sources[0x21]	113	1		T57	3		T79	1		T89	2
valid_sources[0x22]	269	1		T125	1		T162	10		T57	2
valid_sources[0x23]	253	1		T66	1		T57	4		T89	1
valid_sources[0x24]	139	1		T56	13		T57	2		T58	1
valid_sources[0x25]	209	1		T57	2		T58	1		T92	57
valid_sources[0x26]	120	1		T57	2		T58	4		T79	1
valid_sources[0x27]	134	1		T163	1		T56	15		T57	2
valid_sources[0x28]	107	1		T164	2		T165	1		T57	6
valid_sources[0x29]	89	1		T61	2		T57	2		T58	1
valid_sources[0x2a]	124	1		T161	1		T57	5		T58	2
valid_sources[0x2b]	96	1		T166	4		T57	2		T58	1
valid_sources[0x2c]	167	1		T47	1		T66	1		T57	6
valid_sources[0x2d]	89	1		T68	1		T57	4		T58	4
valid_sources[0x2e]	118	1		T167	1		T57	2		T58	3
valid_sources[0x2f]	121	1		T165	3		T57	3		T58	3
valid_sources[0x30]	79	1		T57	2		T79	2		T85	4
valid_sources[0x31]	108	1		T160	1		T57	2		T55	2
valid_sources[0x32]	125	1		T57	3		T58	1		T79	2
valid_sources[0x33]	106	1		T168	2		T57	4		T58	1
valid_sources[0x34]	146	1		T61	3		T56	5		T57	2
valid_sources[0x35]	93	1		T57	2		T58	2		T54	1
valid_sources[0x36]	129	1		T169	1		T170	1		T155	1
valid_sources[0x37]	266	1		T57	4		T58	3		T79	3
valid_sources[0x38]	154	1		T47	1		T161	1		T57	7
valid_sources[0x39]	99	1		T77	1		T57	4		T58	3
valid_sources[0x3a]	102	1		T57	5		T58	3		T79	1
valid_sources[0x3b]	95	1		T57	3		T79	5		T89	1
valid_sources[0x3c]	140	1		T161	2		T56	9		T57	2
valid_sources[0x3d]	403	1		T56	33		T57	2		T58	2
valid_sources[0x3e]	176	1		T56	13		T57	1		T58	5
valid_sources[0x3f]	94	1		T61	2		T57	3		T58	2
valid_sources[0x40]	124	1		T76	4		T57	4		T58	3
valid_sources[0x41]	99	1		T57	2		T58	2		T55	1
valid_sources[0x42]	247	1		T87	1		T57	1		T58	1
valid_sources[0x43]	115	1		T153	1		T164	1		T161	2
valid_sources[0x44]	277	1		T165	1		T57	4		T58	6
valid_sources[0x45]	237	1		T57	4		T58	7		T54	1
valid_sources[0x46]	94	1		T57	2		T58	1		T79	1
valid_sources[0x47]	76	1		T158	1		T171	2		T57	3
valid_sources[0x48]	102	1		T57	3		T58	1		T55	1
valid_sources[0x49]	97	1		T27	1		T57	3		T58	3
valid_sources[0x4a]	296	1		T57	2		T58	4		T55	1
valid_sources[0x4b]	125	1		T57	2		T58	1		T55	1
valid_sources[0x4c]	120	1		T164	1		T57	1		T58	1
valid_sources[0x4d]	100	1		T30	2		T122	1		T58	2
valid_sources[0x4e]	117	1		T163	2		T57	4		T89	2
valid_sources[0x4f]	105	1		T157	2		T57	5		T58	6
valid_sources[0x50]	101	1		T169	1		T57	1		T58	1
valid_sources[0x51]	69	1		T172	2		T58	3		T80	1
valid_sources[0x52]	147	1		T122	2		T173	1		T159	1
valid_sources[0x53]	207	1		T77	1		T58	2		T89	3
valid_sources[0x54]	99	1		T57	1		T79	1		T89	4
valid_sources[0x55]	161	1		T153	1		T56	51		T57	1
valid_sources[0x56]	91	1		T169	1		T57	4		T58	2
valid_sources[0x57]	153	1		T174	1		T56	38		T57	2
valid_sources[0x58]	98	1		T123	1		T171	1		T57	4
valid_sources[0x59]	73	1		T156	1		T58	1		T55	1
valid_sources[0x5a]	122	1		T57	4		T58	2		T89	5
valid_sources[0x5b]	83	1		T58	1		T79	3		T45	8
valid_sources[0x5c]	127	1		T158	2		T57	2		T58	1
valid_sources[0x5d]	101	1		T56	5		T57	1		T58	4
valid_sources[0x5e]	92	1		T57	3		T58	6		T79	1
valid_sources[0x5f]	129	1		T175	3		T56	4		T57	2
valid_sources[0x60]	101	1		T57	6		T58	1		T79	1
valid_sources[0x61]	89	1		T57	4		T58	2		T79	3
valid_sources[0x62]	127	1		T30	1		T158	1		T155	1
valid_sources[0x63]	113	1		T57	5		T58	1		T79	3
valid_sources[0x64]	125	1		T76	15		T176	12		T57	3
valid_sources[0x65]	112	1		T163	1		T56	25		T57	3
valid_sources[0x66]	152	1		T56	16		T57	3		T58	4
valid_sources[0x67]	102	1		T122	1		T170	2		T57	1
valid_sources[0x68]	102	1		T52	3		T171	1		T57	4
valid_sources[0x69]	103	1		T57	2		T58	2		T54	1
valid_sources[0x6a]	114	1		T155	3		T57	2		T58	2
valid_sources[0x6b]	123	1		T169	1		T57	1		T58	2
valid_sources[0x6c]	242	1		T159	2		T56	21		T57	4
valid_sources[0x6d]	107	1		T169	1		T57	3		T58	1
valid_sources[0x6e]	107	1		T57	6		T58	4		T79	3
valid_sources[0x6f]	81	1		T177	1		T57	4		T58	2
valid_sources[0x70]	104	1		T57	2		T58	1		T79	1
valid_sources[0x71]	113	1		T178	1		T57	3		T58	4
valid_sources[0x72]	77	1		T57	4		T58	3		T79	4
valid_sources[0x73]	110	1		T57	3		T79	2		T89	3
valid_sources[0x74]	113	1		T56	21		T57	5		T58	1
valid_sources[0x75]	90	1		T122	1		T57	2		T79	6
valid_sources[0x76]	108	1		T57	3		T79	1		T85	1
valid_sources[0x77]	195	1		T173	7		T159	1		T57	2
valid_sources[0x78]	116	1		T57	2		T58	7		T59	3
valid_sources[0x79]	95	1		T58	3		T79	3		T80	3
valid_sources[0x7a]	128	1		T57	1		T58	3		T79	1
valid_sources[0x7b]	150	1		T56	25		T57	5		T58	2
valid_sources[0x7c]	103	1		T161	1		T58	2		T54	2
valid_sources[0x7d]	99	1		T160	1		T157	1		T57	3
valid_sources[0x7e]	130	1		T3	1		T179	4		T177	1
valid_sources[0x7f]	138	1		T57	4		T58	1		T54	2
valid_sources[0x80]	102	1		T56	7		T57	3		T54	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9170

1

T62

2

T56

161

T57

159

values[0x0]

all_enables

biggest_size

9951

1

T30

1

T47

1

T52

2

values[0x1]

all_enables

biggest_size

9834

1

T48

1

T61

1

T76

1