SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 887568 | 1 | T9 | 9 | T10 | 2 | T6 | 20 | |||
auto[1] | 32752 | 1 | T11 | 80 | T25 | 80 | T56 | 822 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 920111 | 1 | T11 | 80 | T9 | 9 | T10 | 2 | |||
values[1] | 25 | 1 | T54 | 1 | T55 | 1 | T81 | 2 | |||
values[2] | 8 | 1 | T55 | 1 | T81 | 3 | T127 | 2 | |||
values[3] | 107 | 1 | T54 | 3 | T55 | 4 | T81 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 920131 | 1 | T11 | 80 | T9 | 9 | T10 | 2 | |||
values[1] | 27 | 1 | T55 | 1 | T81 | 4 | T127 | 2 | |||
values[2] | 5 | 1 | T130 | 1 | T131 | 1 | T132 | 1 | |||
values[3] | 83 | 1 | T54 | 5 | T55 | 3 | T81 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 920030 | 1 | T11 | 80 | T9 | 9 | T10 | 2 | |||
auto[TlIntgErrCmd] | 101 | 1 | T54 | 2 | T55 | 3 | T81 | 6 | |||
auto[TlIntgErrData] | 81 | 1 | T54 | 4 | T55 | 3 | T81 | 5 | |||
auto[TlIntgErrBoth] | 108 | 1 | T54 | 4 | T55 | 4 | T81 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 64200 | 0 | T3 | 1 | T27 | 1 | T28 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 64021 | 1 | T3 | 1 | T27 | 1 | T28 | 1 | |||
values[1] | 18 | 1 | T54 | 1 | T55 | 1 | T83 | 2 | |||
values[2] | 4 | 1 | T54 | 1 | T127 | 1 | T133 | 1 | |||
values[3] | 98 | 1 | T54 | 2 | T55 | 3 | T81 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 64003 | 1 | T3 | 1 | T27 | 1 | T28 | 1 | |||
values[1] | 18 | 1 | T54 | 1 | T55 | 2 | T81 | 2 | |||
values[2] | 9 | 1 | T55 | 1 | T81 | 1 | T127 | 1 | |||
values[3] | 106 | 1 | T54 | 3 | T55 | 3 | T81 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 63910 | 1 | T3 | 1 | T27 | 1 | T28 | 1 | |||
auto[TlIntgErrCmd] | 93 | 1 | T54 | 1 | T55 | 3 | T81 | 7 | |||
auto[TlIntgErrData] | 111 | 1 | T54 | 5 | T55 | 3 | T81 | 11 | |||
auto[TlIntgErrBoth] | 86 | 1 | T54 | 4 | T55 | 4 | T81 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |