Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	304079	1		T9	5		T10	2		T6	15
full_word	616241	1		T11	80		T9	4		T6	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	920030	1		T11	80		T9	9		T10	2
auto[TlIntgErrCmd]	101	1		T54	2		T55	3		T81	6
auto[TlIntgErrData]	81	1		T54	4		T55	3		T81	5
auto[TlIntgErrBoth]	108	1		T54	4		T55	4		T81	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	544385	1		T11	80		T9	8		T7	6
auto[1]	375935	1		T9	1		T10	2		T6	20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	225891	1		T9	4		T7	3		T8	3
auto[TlIntgErrNone]	partial	auto[1]	77926	1		T9	1		T10	2		T6	15
auto[TlIntgErrNone]	full_word	auto[0]	318366	1		T11	80		T9	4		T7	3
auto[TlIntgErrNone]	full_word	auto[1]	297847	1		T6	5		T7	17		T8	15
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T55	1		T83	3		T127	5
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T54	2		T55	2		T81	5
auto[TlIntgErrCmd]	full_word	auto[0]	10	1		T81	1		T134	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T135	2		T136	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1		T54	3		T81	3		T83	1
auto[TlIntgErrData]	partial	auto[1]	36	1		T54	1		T55	2		T81	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T127	1		T133	1		T137	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T55	1		T127	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T55	1		T81	3		T83	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T54	3		T55	3		T81	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T54	1		T138	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T127	1		T133	1		T131	1