Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.90 96.97 55.32 84.72 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 149451378 24805 0 0
late_debug_enable_rd_A 149451378 2873 0 0
late_debug_enable_regwen_rd_A 149451378 3693 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149451378 24805 0 0
T45 526733 4505 0 0
T54 113576 2 0 0
T55 50987 5 0 0
T56 19499 730 0 0
T57 27268 612 0 0
T58 21421 599 0 0
T79 6749 800 0 0
T80 29340 182 0 0
T81 90746 3 0 0
T82 201796 39 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149451378 2873 0 0
T55 50987 49 0 0
T56 19499 132 0 0
T57 27268 152 0 0
T81 90746 45 0 0
T85 14949 133 0 0
T91 50942 65 0 0
T93 47336 36 0 0
T126 202177 14 0 0
T127 161861 46 0 0
T128 230733 53 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 149451378 3693 0 0
T55 50987 47 0 0
T56 19499 119 0 0
T57 27268 102 0 0
T81 90746 62 0 0
T85 14949 122 0 0
T89 168423 968 0 0
T91 50942 35 0 0
T93 47336 42 0 0
T126 202177 36 0 0
T127 161861 32 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%