Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9513964 |
9512760 |
0 |
0 |
selKnown1 |
72929669 |
72928465 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9513964 |
9512760 |
0 |
0 |
T1 |
14118 |
14116 |
0 |
0 |
T2 |
235268 |
235266 |
0 |
0 |
T3 |
292 |
290 |
0 |
0 |
T4 |
26924 |
26920 |
0 |
0 |
T5 |
20 |
18 |
0 |
0 |
T7 |
0 |
2 |
0 |
0 |
T8 |
0 |
12 |
0 |
0 |
T11 |
234 |
230 |
0 |
0 |
T18 |
0 |
60 |
0 |
0 |
T22 |
2 |
0 |
0 |
0 |
T24 |
25432 |
25428 |
0 |
0 |
T26 |
0 |
10 |
0 |
0 |
T27 |
298 |
296 |
0 |
0 |
T28 |
218 |
214 |
0 |
0 |
T29 |
37818 |
37814 |
0 |
0 |
T30 |
218 |
214 |
0 |
0 |
T40 |
12 |
10 |
0 |
0 |
T49 |
2 |
0 |
0 |
0 |
T51 |
0 |
18 |
0 |
0 |
T71 |
0 |
16 |
0 |
0 |
T72 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72929669 |
72928465 |
0 |
0 |
T1 |
96417 |
96415 |
0 |
0 |
T2 |
396406 |
396405 |
0 |
0 |
T3 |
4831 |
4829 |
0 |
0 |
T4 |
210249 |
210245 |
0 |
0 |
T5 |
20 |
18 |
0 |
0 |
T7 |
0 |
2 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T11 |
2192 |
2188 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T22 |
2 |
0 |
0 |
0 |
T24 |
131797 |
131793 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T27 |
6352 |
6350 |
0 |
0 |
T28 |
6498 |
6494 |
0 |
0 |
T29 |
383007 |
383003 |
0 |
0 |
T30 |
6984 |
6980 |
0 |
0 |
T40 |
12 |
10 |
0 |
0 |
T49 |
2 |
0 |
0 |
0 |
T51 |
0 |
18 |
0 |
0 |
T71 |
0 |
16 |
0 |
0 |
T72 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2744059 |
2743867 |
0 |
0 |
selKnown1 |
66160052 |
66159860 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2744059 |
2743867 |
0 |
0 |
T1 |
7059 |
7058 |
0 |
0 |
T2 |
117634 |
117633 |
0 |
0 |
T3 |
146 |
145 |
0 |
0 |
T4 |
13460 |
13459 |
0 |
0 |
T11 |
116 |
115 |
0 |
0 |
T24 |
12715 |
12714 |
0 |
0 |
T27 |
149 |
148 |
0 |
0 |
T28 |
108 |
107 |
0 |
0 |
T29 |
18908 |
18907 |
0 |
0 |
T30 |
108 |
107 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
66160052 |
66159860 |
0 |
0 |
T1 |
89358 |
89357 |
0 |
0 |
T2 |
278772 |
278772 |
0 |
0 |
T3 |
4685 |
4684 |
0 |
0 |
T4 |
196785 |
196784 |
0 |
0 |
T11 |
2074 |
2073 |
0 |
0 |
T24 |
119080 |
119079 |
0 |
0 |
T27 |
6203 |
6202 |
0 |
0 |
T28 |
6388 |
6387 |
0 |
0 |
T29 |
364097 |
364096 |
0 |
0 |
T30 |
6874 |
6873 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
586 |
394 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T18 |
0 |
28 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T40 |
6 |
5 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
9 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
506 |
314 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T40 |
6 |
5 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
9 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6767532 |
6767122 |
0 |
0 |
selKnown1 |
6767532 |
6767122 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6767532 |
6767122 |
0 |
0 |
T1 |
7059 |
7058 |
0 |
0 |
T2 |
117634 |
117633 |
0 |
0 |
T3 |
146 |
145 |
0 |
0 |
T4 |
13460 |
13459 |
0 |
0 |
T11 |
116 |
115 |
0 |
0 |
T24 |
12715 |
12714 |
0 |
0 |
T27 |
149 |
148 |
0 |
0 |
T28 |
108 |
107 |
0 |
0 |
T29 |
18908 |
18907 |
0 |
0 |
T30 |
108 |
107 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6767532 |
6767122 |
0 |
0 |
T1 |
7059 |
7058 |
0 |
0 |
T2 |
117634 |
117633 |
0 |
0 |
T3 |
146 |
145 |
0 |
0 |
T4 |
13460 |
13459 |
0 |
0 |
T11 |
116 |
115 |
0 |
0 |
T24 |
12715 |
12714 |
0 |
0 |
T27 |
149 |
148 |
0 |
0 |
T28 |
108 |
107 |
0 |
0 |
T29 |
18908 |
18907 |
0 |
0 |
T30 |
108 |
107 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1787 |
1377 |
0 |
0 |
selKnown1 |
1579 |
1169 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1787 |
1377 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
7 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T18 |
0 |
32 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T26 |
0 |
6 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T40 |
6 |
5 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
9 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1579 |
1169 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
10 |
9 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T40 |
6 |
5 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
9 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |