SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
58.07 | 78.43 | 66.67 | 28.57 | 66.67 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1152 | 1152 | 0 | 0 |
OutputsKnown_A | 396960312 | 396758208 | 0 | 0 |
gen_flops.OutputDelay_A | 198480156 | 198374550 | 0 | 1728 |
gen_no_flops.OutputDelay_A | 198480156 | 198379104 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1152 | 1152 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T28 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
T30 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396960312 | 396758208 | 0 | 0 |
T1 | 536148 | 535644 | 0 | 0 |
T2 | 1672632 | 1672602 | 0 | 0 |
T3 | 28110 | 27708 | 0 | 0 |
T4 | 1180710 | 1179738 | 0 | 0 |
T11 | 12444 | 12054 | 0 | 0 |
T24 | 714480 | 714066 | 0 | 0 |
T27 | 37218 | 36804 | 0 | 0 |
T28 | 38328 | 38010 | 0 | 0 |
T29 | 2184582 | 2184168 | 0 | 0 |
T30 | 41244 | 40860 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198480156 | 198374550 | 0 | 1728 |
T1 | 268074 | 267813 | 0 | 9 |
T2 | 836316 | 836301 | 0 | 9 |
T3 | 14055 | 13845 | 0 | 9 |
T4 | 590355 | 589851 | 0 | 9 |
T11 | 6222 | 6018 | 0 | 9 |
T24 | 357240 | 357024 | 0 | 9 |
T27 | 18609 | 18393 | 0 | 9 |
T28 | 19164 | 18996 | 0 | 9 |
T29 | 1092291 | 1092075 | 0 | 9 |
T30 | 20622 | 20421 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198480156 | 198379104 | 0 | 0 |
T1 | 268074 | 267822 | 0 | 0 |
T2 | 836316 | 836301 | 0 | 0 |
T3 | 14055 | 13854 | 0 | 0 |
T4 | 590355 | 589869 | 0 | 0 |
T11 | 6222 | 6027 | 0 | 0 |
T24 | 357240 | 357033 | 0 | 0 |
T27 | 18609 | 18402 | 0 | 0 |
T28 | 19164 | 19005 | 0 | 0 |
T29 | 1092291 | 1092084 | 0 | 0 |
T30 | 20622 | 20430 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 192 | 192 | 0 | 0 |
OutputsKnown_A | 66160052 | 66126368 | 0 | 0 |
gen_flops.OutputDelay_A | 66160052 | 66124850 | 0 | 576 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192 | 192 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66124850 | 0 | 576 |
T1 | 89358 | 89271 | 0 | 3 |
T2 | 278772 | 278767 | 0 | 3 |
T3 | 4685 | 4615 | 0 | 3 |
T4 | 196785 | 196617 | 0 | 3 |
T11 | 2074 | 2006 | 0 | 3 |
T24 | 119080 | 119008 | 0 | 3 |
T27 | 6203 | 6131 | 0 | 3 |
T28 | 6388 | 6332 | 0 | 3 |
T29 | 364097 | 364025 | 0 | 3 |
T30 | 6874 | 6807 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 192 | 192 | 0 | 0 |
OutputsKnown_A | 66160052 | 66126368 | 0 | 0 |
gen_flops.OutputDelay_A | 66160052 | 66124850 | 0 | 576 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192 | 192 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66124850 | 0 | 576 |
T1 | 89358 | 89271 | 0 | 3 |
T2 | 278772 | 278767 | 0 | 3 |
T3 | 4685 | 4615 | 0 | 3 |
T4 | 196785 | 196617 | 0 | 3 |
T11 | 2074 | 2006 | 0 | 3 |
T24 | 119080 | 119008 | 0 | 3 |
T27 | 6203 | 6131 | 0 | 3 |
T28 | 6388 | 6332 | 0 | 3 |
T29 | 364097 | 364025 | 0 | 3 |
T30 | 6874 | 6807 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 192 | 192 | 0 | 0 |
OutputsKnown_A | 66160052 | 66126368 | 0 | 0 |
gen_no_flops.OutputDelay_A | 66160052 | 66126368 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192 | 192 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 192 | 192 | 0 | 0 |
OutputsKnown_A | 66160052 | 66126368 | 0 | 0 |
gen_flops.OutputDelay_A | 66160052 | 66124850 | 0 | 576 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192 | 192 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66124850 | 0 | 576 |
T1 | 89358 | 89271 | 0 | 3 |
T2 | 278772 | 278767 | 0 | 3 |
T3 | 4685 | 4615 | 0 | 3 |
T4 | 196785 | 196617 | 0 | 3 |
T11 | 2074 | 2006 | 0 | 3 |
T24 | 119080 | 119008 | 0 | 3 |
T27 | 6203 | 6131 | 0 | 3 |
T28 | 6388 | 6332 | 0 | 3 |
T29 | 364097 | 364025 | 0 | 3 |
T30 | 6874 | 6807 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 192 | 192 | 0 | 0 |
OutputsKnown_A | 66160052 | 66126368 | 0 | 0 |
gen_no_flops.OutputDelay_A | 66160052 | 66126368 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192 | 192 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 192 | 192 | 0 | 0 |
OutputsKnown_A | 66160052 | 66126368 | 0 | 0 |
gen_no_flops.OutputDelay_A | 66160052 | 66126368 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192 | 192 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 66160052 | 66126368 | 0 | 0 |
T1 | 89358 | 89274 | 0 | 0 |
T2 | 278772 | 278767 | 0 | 0 |
T3 | 4685 | 4618 | 0 | 0 |
T4 | 196785 | 196623 | 0 | 0 |
T11 | 2074 | 2009 | 0 | 0 |
T24 | 119080 | 119011 | 0 | 0 |
T27 | 6203 | 6134 | 0 | 0 |
T28 | 6388 | 6335 | 0 | 0 |
T29 | 364097 | 364028 | 0 | 0 |
T30 | 6874 | 6810 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |