Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 181470 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 489570 1 T2 4 T4 1 T7 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 425879 1 T20 10 T16 10 T17 6
values[0x0] 118904 1 T2 6 T4 1 T7 4
values[0x1] 126257 1 T2 8 T7 3 T14 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 136067 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 534973 1 T2 4 T4 1 T7 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2018 1 T16 2 T39 1 T46 1
valid_sources[0x01] 2514 1 T16 2 T42 1 T36 1
valid_sources[0x02] 2491 1 T16 3 T39 1 T146 1
valid_sources[0x03] 3235 1 T16 1 T39 1 T40 1
valid_sources[0x04] 2755 1 T147 3 T148 3 T149 2
valid_sources[0x05] 2396 1 T44 2 T150 1 T151 1
valid_sources[0x06] 2722 1 T16 1 T39 1 T149 1
valid_sources[0x07] 2521 1 T149 1 T60 2 T62 4
valid_sources[0x08] 2809 1 T149 2 T62 14 T61 18
valid_sources[0x09] 2623 1 T26 1 T149 2 T62 4
valid_sources[0x0a] 2370 1 T10 2 T16 3 T47 2
valid_sources[0x0b] 2597 1 T40 1 T60 14 T62 17
valid_sources[0x0c] 2241 1 T10 1 T11 1 T147 1
valid_sources[0x0d] 2335 1 T147 1 T40 1 T146 1
valid_sources[0x0e] 3124 1 T16 2 T36 1 T147 1
valid_sources[0x0f] 2216 1 T10 1 T84 2 T40 2
valid_sources[0x10] 2898 1 T10 3 T16 2 T28 1
valid_sources[0x11] 2952 1 T26 1 T151 1 T146 1
valid_sources[0x12] 2593 1 T36 3 T149 1 T44 1
valid_sources[0x13] 2410 1 T36 5 T150 1 T60 13
valid_sources[0x14] 2939 1 T45 2 T40 2 T151 1
valid_sources[0x15] 2537 1 T16 3 T42 1 T60 12
valid_sources[0x16] 2360 1 T14 3 T40 3 T48 1
valid_sources[0x17] 2182 1 T16 1 T60 18 T62 22
valid_sources[0x18] 2101 1 T10 1 T36 2 T46 2
valid_sources[0x19] 2543 1 T152 1 T40 3 T60 9
valid_sources[0x1a] 3937 1 T147 1 T40 1 T151 2
valid_sources[0x1b] 2471 1 T16 2 T36 1 T39 2
valid_sources[0x1c] 2661 1 T16 1 T149 1 T151 1
valid_sources[0x1d] 2486 1 T16 2 T39 1 T60 40
valid_sources[0x1e] 2853 1 T36 1 T149 1 T44 1
valid_sources[0x1f] 2418 1 T26 2 T44 1 T60 15
valid_sources[0x20] 3847 1 T36 1 T151 1 T60 11
valid_sources[0x21] 2324 1 T4 1 T16 1 T11 1
valid_sources[0x22] 2858 1 T39 1 T151 1 T146 2
valid_sources[0x23] 2622 1 T84 1 T40 1 T62 17
valid_sources[0x24] 2075 1 T17 1 T36 1 T46 3
valid_sources[0x25] 2851 1 T36 1 T40 5 T149 2
valid_sources[0x26] 2675 1 T17 1 T36 2 T149 1
valid_sources[0x27] 2558 1 T147 3 T152 1 T151 1
valid_sources[0x28] 2462 1 T40 1 T151 2 T146 1
valid_sources[0x29] 2178 1 T84 1 T146 1 T60 23
valid_sources[0x2a] 2877 1 T16 1 T36 2 T39 1
valid_sources[0x2b] 2353 1 T47 2 T151 1 T60 2
valid_sources[0x2c] 2845 1 T36 1 T40 1 T151 1
valid_sources[0x2d] 2072 1 T11 2 T147 2 T40 1
valid_sources[0x2e] 2272 1 T2 14 T39 2 T84 1
valid_sources[0x2f] 3520 1 T11 1 T147 1 T152 1
valid_sources[0x30] 2262 1 T10 1 T26 2 T153 1
valid_sources[0x31] 2540 1 T16 2 T146 1 T62 18
valid_sources[0x32] 2396 1 T154 1 T60 1 T62 4
valid_sources[0x33] 2673 1 T10 1 T36 2 T152 2
valid_sources[0x34] 2572 1 T39 1 T44 3 T151 1
valid_sources[0x35] 4057 1 T36 1 T84 1 T40 3
valid_sources[0x36] 2856 1 T146 2 T60 10 T62 9
valid_sources[0x37] 2660 1 T149 1 T146 1 T62 17
valid_sources[0x38] 3350 1 T10 1 T11 1 T36 1
valid_sources[0x39] 2570 1 T7 3 T47 1 T39 1
valid_sources[0x3a] 2473 1 T16 3 T26 1 T42 2
valid_sources[0x3b] 2100 1 T36 1 T44 1 T60 8
valid_sources[0x3c] 2743 1 T20 1 T148 1 T84 1
valid_sources[0x3d] 2832 1 T16 3 T36 2 T84 1
valid_sources[0x3e] 2516 1 T155 4 T62 7 T61 31
valid_sources[0x3f] 2196 1 T20 6 T17 2 T40 3
valid_sources[0x40] 2742 1 T6 4 T10 2 T16 1
valid_sources[0x41] 2535 1 T154 1 T11 3 T84 2
valid_sources[0x42] 2720 1 T11 1 T84 1 T44 1
valid_sources[0x43] 2450 1 T26 3 T11 1 T39 1
valid_sources[0x44] 2473 1 T16 2 T42 1 T40 1
valid_sources[0x45] 2622 1 T16 1 T11 1 T149 1
valid_sources[0x46] 2184 1 T42 1 T36 1 T60 15
valid_sources[0x47] 2849 1 T36 1 T149 1 T151 1
valid_sources[0x48] 2774 1 T10 1 T60 8 T62 13
valid_sources[0x49] 2156 1 T16 2 T17 1 T84 2
valid_sources[0x4a] 2135 1 T16 1 T36 3 T39 2
valid_sources[0x4b] 3028 1 T147 1 T151 1 T146 1
valid_sources[0x4c] 2303 1 T150 1 T151 1 T60 5
valid_sources[0x4d] 2641 1 T26 1 T147 1 T39 1
valid_sources[0x4e] 2062 1 T148 4 T62 20 T61 14
valid_sources[0x4f] 2156 1 T26 1 T151 1 T60 2
valid_sources[0x50] 2550 1 T17 1 T146 2 T60 24
valid_sources[0x51] 3715 1 T11 1 T150 1 T60 36
valid_sources[0x52] 2423 1 T10 1 T16 7 T11 1
valid_sources[0x53] 2458 1 T147 1 T40 1 T46 4
valid_sources[0x54] 2191 1 T18 4 T10 1 T11 1
valid_sources[0x55] 2204 1 T36 1 T40 2 T155 5
valid_sources[0x56] 2482 1 T10 2 T147 1 T40 1
valid_sources[0x57] 2493 1 T36 3 T40 1 T149 1
valid_sources[0x58] 2120 1 T40 1 T60 2 T62 4
valid_sources[0x59] 2012 1 T151 1 T60 3 T62 24
valid_sources[0x5a] 2138 1 T39 1 T150 1 T146 1
valid_sources[0x5b] 2384 1 T146 1 T60 1 T62 17
valid_sources[0x5c] 2274 1 T16 1 T62 31 T61 12
valid_sources[0x5d] 2250 1 T26 1 T11 1 T148 1
valid_sources[0x5e] 2765 1 T16 1 T36 3 T48 2
valid_sources[0x5f] 2544 1 T146 3 T62 12 T61 30
valid_sources[0x60] 2546 1 T26 1 T147 1 T149 2
valid_sources[0x61] 2834 1 T7 1 T16 3 T17 1
valid_sources[0x62] 3365 1 T7 2 T16 2 T17 1
valid_sources[0x63] 2341 1 T10 2 T36 1 T39 1
valid_sources[0x64] 2149 1 T155 4 T151 1 T62 10
valid_sources[0x65] 2345 1 T147 1 T39 1 T40 4
valid_sources[0x66] 2523 1 T16 1 T17 2 T41 1
valid_sources[0x67] 2435 1 T26 1 T39 1 T84 2
valid_sources[0x68] 3436 1 T10 1 T16 6 T39 1
valid_sources[0x69] 2590 1 T36 2 T60 12 T62 6
valid_sources[0x6a] 2745 1 T5 1 T44 2 T151 1
valid_sources[0x6b] 2166 1 T10 1 T47 1 T44 2
valid_sources[0x6c] 2616 1 T10 2 T36 1 T39 2
valid_sources[0x6d] 3614 1 T36 2 T39 1 T40 1
valid_sources[0x6e] 3788 1 T16 2 T40 1 T146 1
valid_sources[0x6f] 2313 1 T16 1 T11 1 T149 1
valid_sources[0x70] 2208 1 T60 11 T62 19 T54 2
valid_sources[0x71] 2444 1 T10 2 T36 1 T147 3
valid_sources[0x72] 2123 1 T40 1 T146 2 T60 1
valid_sources[0x73] 2947 1 T16 2 T84 2 T62 4
valid_sources[0x74] 2749 1 T16 1 T151 1 T60 2
valid_sources[0x75] 2519 1 T16 7 T84 2 T40 1
valid_sources[0x76] 2611 1 T42 1 T147 1 T149 1
valid_sources[0x77] 1967 1 T39 1 T40 1 T60 2
valid_sources[0x78] 2089 1 T16 1 T40 1 T150 1
valid_sources[0x79] 2148 1 T84 1 T40 5 T60 4
valid_sources[0x7a] 2351 1 T11 2 T149 1 T150 1
valid_sources[0x7b] 2750 1 T36 1 T62 25 T54 4
valid_sources[0x7c] 2312 1 T10 3 T11 1 T40 1
valid_sources[0x7d] 2357 1 T60 1 T62 12 T61 14
valid_sources[0x7e] 2467 1 T12 61 T40 1 T150 1
valid_sources[0x7f] 2670 1 T16 4 T40 1 T44 1
valid_sources[0x80] 3676 1 T45 1 T21 2 T40 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 256554 1 T20 5 T16 4 T17 1
values[0x0] all_enables biggest_size 116821 1 T2 3 T4 1 T14 1
values[0x1] all_enables biggest_size 116195 1 T2 1 T7 1 T14 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4220 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 29814 1 T32 1 T50 2 T58 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 11230 1 T60 52 T62 21 T61 65
values[0x0] 11126 1 T32 6 T50 3 T51 4
values[0x1] 11678 1 T32 3 T51 4 T58 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3075 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 30959 1 T32 1 T50 2 T51 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 93 1 T97 1 T54 5 T74 1
valid_sources[0x01] 115 1 T60 1 T62 3 T54 1
valid_sources[0x02] 102 1 T156 1 T157 1 T60 1
valid_sources[0x03] 91 1 T60 1 T54 6 T81 6
valid_sources[0x04] 151 1 T158 3 T159 2 T160 1
valid_sources[0x05] 99 1 T54 5 T80 1 T81 1
valid_sources[0x06] 111 1 T161 1 T60 1 T54 6
valid_sources[0x07] 85 1 T162 1 T54 5 T80 3
valid_sources[0x08] 94 1 T132 1 T54 2 T74 1
valid_sources[0x09] 141 1 T163 1 T54 4 T75 1
valid_sources[0x0a] 93 1 T164 3 T54 2 T74 1
valid_sources[0x0b] 100 1 T97 1 T164 3 T165 1
valid_sources[0x0c] 192 1 T61 3 T54 2 T81 4
valid_sources[0x0d] 93 1 T54 7 T74 1 T80 1
valid_sources[0x0e] 170 1 T166 1 T62 1 T61 5
valid_sources[0x0f] 185 1 T156 1 T165 1 T62 1
valid_sources[0x10] 95 1 T97 1 T167 1 T54 4
valid_sources[0x11] 147 1 T163 1 T54 8 T74 1
valid_sources[0x12] 380 1 T168 1 T60 2 T54 7
valid_sources[0x13] 152 1 T77 1 T168 1 T60 2
valid_sources[0x14] 129 1 T97 2 T60 3 T54 6
valid_sources[0x15] 97 1 T54 4 T80 1 T81 5
valid_sources[0x16] 100 1 T61 7 T54 6 T80 1
valid_sources[0x17] 117 1 T158 6 T60 2 T54 1
valid_sources[0x18] 110 1 T169 1 T170 1 T61 5
valid_sources[0x19] 190 1 T77 1 T54 1 T72 68
valid_sources[0x1a] 172 1 T132 1 T60 1 T54 4
valid_sources[0x1b] 202 1 T132 1 T54 7 T80 3
valid_sources[0x1c] 167 1 T161 1 T54 8 T74 1
valid_sources[0x1d] 166 1 T60 1 T54 7 T74 1
valid_sources[0x1e] 279 1 T171 1 T54 6 T80 5
valid_sources[0x1f] 238 1 T163 1 T60 1 T54 6
valid_sources[0x20] 125 1 T58 1 T172 1 T60 2
valid_sources[0x21] 139 1 T77 1 T60 1 T54 4
valid_sources[0x22] 129 1 T158 1 T60 1 T62 1
valid_sources[0x23] 97 1 T97 2 T60 1 T62 1
valid_sources[0x24] 79 1 T156 1 T54 6 T80 1
valid_sources[0x25] 130 1 T173 2 T163 1 T170 1
valid_sources[0x26] 88 1 T61 1 T54 3 T80 4
valid_sources[0x27] 91 1 T163 1 T54 8 T74 1
valid_sources[0x28] 235 1 T54 3 T74 1 T75 1
valid_sources[0x29] 107 1 T60 1 T54 6 T80 1
valid_sources[0x2a] 106 1 T173 1 T62 1 T54 6
valid_sources[0x2b] 78 1 T78 1 T156 1 T60 1
valid_sources[0x2c] 95 1 T161 1 T165 2 T61 3
valid_sources[0x2d] 149 1 T60 2 T54 4 T74 1
valid_sources[0x2e] 126 1 T169 1 T174 8 T54 8
valid_sources[0x2f] 278 1 T61 3 T54 3 T80 1
valid_sources[0x30] 145 1 T161 2 T162 1 T60 3
valid_sources[0x31] 88 1 T162 1 T60 1 T54 4
valid_sources[0x32] 214 1 T78 1 T157 1 T168 1
valid_sources[0x33] 93 1 T175 4 T176 3 T54 6
valid_sources[0x34] 130 1 T163 1 T74 1 T75 2
valid_sources[0x35] 101 1 T158 1 T161 1 T60 2
valid_sources[0x36] 132 1 T173 1 T170 1 T60 1
valid_sources[0x37] 122 1 T77 1 T163 1 T60 1
valid_sources[0x38] 166 1 T58 2 T177 10 T60 1
valid_sources[0x39] 135 1 T60 1 T62 1 T54 8
valid_sources[0x3a] 128 1 T161 1 T54 5 T74 1
valid_sources[0x3b] 77 1 T169 1 T60 2 T54 3
valid_sources[0x3c] 143 1 T168 2 T173 1 T60 2
valid_sources[0x3d] 89 1 T32 1 T97 2 T168 1
valid_sources[0x3e] 135 1 T32 1 T178 1 T62 1
valid_sources[0x3f] 109 1 T161 2 T54 5 T74 1
valid_sources[0x40] 109 1 T132 1 T169 1 T171 2
valid_sources[0x41] 124 1 T179 4 T54 6 T81 2
valid_sources[0x42] 117 1 T168 1 T54 1 T74 1
valid_sources[0x43] 93 1 T54 8 T74 1 T83 1
valid_sources[0x44] 131 1 T172 1 T54 6 T88 1
valid_sources[0x45] 171 1 T97 2 T60 1 T62 1
valid_sources[0x46] 112 1 T158 1 T54 2 T74 1
valid_sources[0x47] 83 1 T60 2 T54 4 T80 2
valid_sources[0x48] 136 1 T157 8 T60 1 T54 2
valid_sources[0x49] 104 1 T60 1 T62 1 T54 7
valid_sources[0x4a] 220 1 T178 1 T175 1 T60 1
valid_sources[0x4b] 104 1 T76 1 T170 1 T54 2
valid_sources[0x4c] 132 1 T163 1 T54 8 T80 2
valid_sources[0x4d] 121 1 T159 1 T54 3 T74 1
valid_sources[0x4e] 167 1 T178 1 T173 1 T54 8
valid_sources[0x4f] 98 1 T60 1 T54 8 T80 1
valid_sources[0x50] 105 1 T132 1 T180 1 T62 1
valid_sources[0x51] 112 1 T32 1 T77 3 T178 1
valid_sources[0x52] 311 1 T174 5 T54 6 T74 2
valid_sources[0x53] 117 1 T181 6 T54 3 T81 8
valid_sources[0x54] 95 1 T182 5 T60 2 T54 5
valid_sources[0x55] 98 1 T173 1 T60 2 T54 2
valid_sources[0x56] 171 1 T58 1 T60 1 T54 9
valid_sources[0x57] 96 1 T54 5 T86 1 T82 1
valid_sources[0x58] 135 1 T183 1 T62 1 T54 6
valid_sources[0x59] 101 1 T132 1 T54 1 T73 11
valid_sources[0x5a] 82 1 T54 6 T74 1 T80 2
valid_sources[0x5b] 120 1 T60 1 T61 5 T54 7
valid_sources[0x5c] 119 1 T132 3 T54 5 T73 5
valid_sources[0x5d] 93 1 T172 1 T60 1 T62 1
valid_sources[0x5e] 100 1 T161 1 T60 1 T54 8
valid_sources[0x5f] 114 1 T173 1 T54 6 T74 1
valid_sources[0x60] 91 1 T159 1 T178 1 T54 5
valid_sources[0x61] 126 1 T54 3 T81 13 T88 1
valid_sources[0x62] 147 1 T171 7 T168 1 T54 4
valid_sources[0x63] 116 1 T32 1 T172 1 T178 1
valid_sources[0x64] 162 1 T77 3 T95 2 T54 3
valid_sources[0x65] 276 1 T54 6 T75 2 T80 2
valid_sources[0x66] 119 1 T180 2 T60 1 T54 6
valid_sources[0x67] 149 1 T161 1 T54 3 T74 3
valid_sources[0x68] 224 1 T58 1 T169 2 T60 1
valid_sources[0x69] 111 1 T180 1 T60 1 T54 5
valid_sources[0x6a] 128 1 T163 1 T60 1 T54 6
valid_sources[0x6b] 223 1 T60 1 T54 4 T75 2
valid_sources[0x6c] 91 1 T60 3 T54 7 T74 2
valid_sources[0x6d] 97 1 T176 1 T54 11 T80 2
valid_sources[0x6e] 105 1 T174 1 T54 6 T81 8
valid_sources[0x6f] 93 1 T132 1 T54 3 T75 1
valid_sources[0x70] 89 1 T60 2 T54 10 T81 1
valid_sources[0x71] 175 1 T170 2 T54 4 T74 1
valid_sources[0x72] 214 1 T62 1 T54 4 T72 44
valid_sources[0x73] 136 1 T63 1 T60 2 T62 1
valid_sources[0x74] 68 1 T175 1 T61 3 T54 1
valid_sources[0x75] 98 1 T80 2 T81 4 T82 1
valid_sources[0x76] 95 1 T60 1 T54 3 T80 2
valid_sources[0x77] 132 1 T54 5 T75 1 T80 1
valid_sources[0x78] 157 1 T54 5 T74 1 T80 2
valid_sources[0x79] 80 1 T157 1 T60 1 T62 1
valid_sources[0x7a] 136 1 T183 1 T54 3 T74 1
valid_sources[0x7b] 99 1 T183 1 T184 28 T56 15
valid_sources[0x7c] 131 1 T62 1 T54 6 T80 2
valid_sources[0x7d] 121 1 T161 1 T54 6 T75 2
valid_sources[0x7e] 147 1 T97 1 T60 1 T54 6
valid_sources[0x7f] 120 1 T176 1 T60 1 T54 2
valid_sources[0x80] 80 1 T166 1 T54 5 T74 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 8905 1 T60 44 T62 21 T61 26
values[0x0] all_enables biggest_size 10469 1 T32 1 T50 2 T58 1
values[0x1] all_enables biggest_size 10440 1 T58 1 T63 1 T77 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%