Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
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Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 0 2 100.00 100 1 1 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0



Group Instance : tl_intg_err_cgs_wrap[rv_dm_regs_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[rv_dm_regs_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[rv_dm_regs_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 708235 1 T2 14 T4 1 T7 7
auto[1] 36086 1 T36 80 T37 80 T60 74



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 744139 1 T2 14 T4 1 T7 7
values[1] 15 1 T74 2 T75 1 T83 2
values[2] 3 1 T75 1 T134 1 T135 1
values[3] 88 1 T61 9 T74 5 T75 3



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 744153 1 T2 14 T4 1 T7 7
values[1] 16 1 T61 1 T74 2 T83 1
values[2] 4 1 T75 1 T136 1 T137 1
values[3] 83 1 T61 7 T74 7 T75 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 744051 1 T2 14 T4 1 T7 7
auto[TlIntgErrCmd] 102 1 T61 8 T74 9 T75 1
auto[TlIntgErrData] 88 1 T61 6 T74 6 T75 3
auto[TlIntgErrBoth] 80 1 T61 6 T74 5 T75 6


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 65130 0 T32 9 T50 3 T51 8



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 64947 1 T32 9 T50 3 T51 8
values[1] 23 1 T61 2 T74 2 T75 1
values[2] 3 1 T74 1 T138 1 T139 1
values[3] 104 1 T61 5 T74 5 T75 1



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 64951 1 T32 9 T50 3 T51 8
values[1] 11 1 T61 2 T74 2 T75 1
values[2] 6 1 T61 1 T83 1 T140 1
values[3] 90 1 T61 8 T74 6 T75 3



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 64860 1 T32 9 T50 3 T51 8
auto[TlIntgErrCmd] 91 1 T61 4 T74 7 T75 2
auto[TlIntgErrData] 87 1 T61 9 T74 6 T75 6
auto[TlIntgErrBoth] 92 1 T61 7 T74 7 T75 2

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