Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	251422	1		T2	10		T7	6		T14	1
full_word	492899	1		T2	4		T4	1		T7	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	744051	1		T2	14		T4	1		T7	7
auto[TlIntgErrCmd]	102	1		T61	8		T74	9		T75	1
auto[TlIntgErrData]	88	1		T61	6		T74	6		T75	3
auto[TlIntgErrBoth]	80	1		T61	6		T74	5		T75	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	429885	1		T20	10		T16	10		T17	6
auto[1]	314436	1		T2	14		T4	1		T7	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	172765	1		T20	5		T16	6		T17	5
auto[TlIntgErrNone]	partial	auto[1]	78410	1		T2	10		T7	6		T14	1
auto[TlIntgErrNone]	full_word	auto[0]	256991	1		T20	5		T16	4		T17	1
auto[TlIntgErrNone]	full_word	auto[1]	235885	1		T2	4		T4	1		T7	1
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T61	3		T74	5		T83	6
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T61	3		T74	4		T75	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T61	2		T141	1		T137	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T142	1		T139	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1		T61	1		T74	3		T75	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T61	5		T74	3		T75	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T136	1		T138	1		T137	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T83	1		T143	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T61	1		T74	1		T75	3
auto[TlIntgErrBoth]	partial	auto[1]	40	1		T61	4		T74	2		T75	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T75	1		T83	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T61	1		T74	2		T140	1