Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.85	96.97	55.32	89.47		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	174715918	24680	0	0
late_debug_enable_rd_A	174715918	2810	0	0
late_debug_enable_regwen_rd_A	174715918	3023	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174715918	24680	0	0
T54	150798	1068	0	0
T60	219595	59	0	0
T61	173101	2	0	0
T72	209202	69	0	0
T73	3885	125	0	0
T74	105895	5	0	0
T75	94541	1	0	0
T80	13807	293	0	0
T81	169651	210	0	0
T82	24262	240	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174715918	2810	0	0
T55	695362	169	0	0
T60	219595	56	0	0
T92	4647	5	0	0
T93	8782	3	0	0
T106	365460	115	0	0
T108	28988	15	0	0
T109	26435	47	0	0
T110	8207	9	0	0
T130	167217	34	0	0
T131	399466	40	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174715918	3023	0	0
T55	695362	144	0	0
T60	219595	76	0	0
T92	4647	3	0	0
T93	8782	2	0	0
T106	365460	185	0	0
T108	28988	12	0	0
T109	26435	9	0	0
T110	8207	4	0	0
T130	167217	19	0	0
T131	399466	22	0	0