Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10354987 10353763 0 0
selKnown1 77026778 77025554 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10354987 10353763 0 0
T1 2696 2692 0 0
T2 8982 8978 0 0
T3 31164 31160 0 0
T4 44836 44832 0 0
T5 0 28 0 0
T9 38476 38472 0 0
T13 31328 31324 0 0
T15 32016 32012 0 0
T23 0 4 0 0
T30 21748 21744 0 0
T31 27064 27060 0 0
T32 284 280 0 0
T38 0 4 0 0
T52 0 20 0 0
T53 0 20 0 0
T57 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 77026778 77025554 0 0
T1 33177 33173 0 0
T2 65972 65968 0 0
T3 552798 552794 0 0
T4 607809 607805 0 0
T5 0 4 0 0
T9 135173 135170 0 0
T13 57742 57738 0 0
T15 165638 165634 0 0
T23 0 4 0 0
T30 106571 106567 0 0
T31 127053 127050 0 0
T32 1911 1907 0 0
T38 0 4 0 0
T52 0 20 0 0
T53 0 20 0 0
T57 0 4 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3239171 3238975 0 0
selKnown1 69911337 69911141 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3239171 3238975 0 0
T1 1337 1336 0 0
T2 4490 4489 0 0
T3 15581 15580 0 0
T4 22408 22407 0 0
T9 19237 19236 0 0
T13 15657 15656 0 0
T15 16003 16002 0 0
T30 10873 10872 0 0
T31 13531 13530 0 0
T32 141 140 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 69911337 69911141 0 0
T1 31818 31817 0 0
T2 61480 61479 0 0
T3 537215 537214 0 0
T4 585393 585392 0 0
T9 115934 115934 0 0
T13 42071 42070 0 0
T15 149625 149624 0 0
T30 95696 95695 0 0
T31 113520 113520 0 0
T32 1768 1767 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 524 328 0 0
selKnown1 461 265 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 524 328 0 0
T1 11 10 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 14 0 0
T9 1 0 0 0
T13 7 6 0 0
T15 5 4 0 0
T23 0 2 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T38 0 2 0 0
T52 0 10 0 0
T53 0 10 0 0
T57 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 461 265 0 0
T1 11 10 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 2 0 0
T9 1 0 0 0
T13 7 6 0 0
T15 5 4 0 0
T23 0 2 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T38 0 2 0 0
T52 0 10 0 0
T53 0 10 0 0
T57 0 2 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7113377 7112961 0 0
selKnown1 7113377 7112961 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7113377 7112961 0 0
T1 1337 1336 0 0
T2 4490 4489 0 0
T3 15581 15580 0 0
T4 22408 22407 0 0
T9 19237 19236 0 0
T13 15657 15656 0 0
T15 16003 16002 0 0
T30 10873 10872 0 0
T31 13531 13530 0 0
T32 141 140 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 7113377 7112961 0 0
T1 1337 1336 0 0
T2 4490 4489 0 0
T3 15581 15580 0 0
T4 22408 22407 0 0
T9 19237 19236 0 0
T13 15657 15656 0 0
T15 16003 16002 0 0
T30 10873 10872 0 0
T31 13531 13530 0 0
T32 141 140 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1915 1499 0 0
selKnown1 1603 1187 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1915 1499 0 0
T1 11 10 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 16 15 0 0
T5 0 14 0 0
T9 1 0 0 0
T13 7 6 0 0
T15 5 4 0 0
T23 0 2 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T38 0 2 0 0
T52 0 10 0 0
T53 0 10 0 0
T57 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1603 1187 0 0
T1 11 10 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 4 3 0 0
T5 0 2 0 0
T9 1 0 0 0
T13 7 6 0 0
T15 5 4 0 0
T23 0 2 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T38 0 2 0 0
T52 0 10 0 0
T53 0 10 0 0
T57 0 2 0 0

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