SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.85 | 96.97 | 55.32 | 89.47 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 196 | 196 | 0 | 0 |
OutputsKnown_A | 69911337 | 69880586 | 0 | 0 |
gen_no_flops.OutputDelay_A | 69911337 | 69880586 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 196 | 196 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 69911337 | 69880586 | 0 | 0 |
T1 | 31818 | 31141 | 0 | 0 |
T2 | 61480 | 61421 | 0 | 0 |
T3 | 537215 | 537119 | 0 | 0 |
T4 | 585393 | 585143 | 0 | 0 |
T9 | 115934 | 115928 | 0 | 0 |
T13 | 42071 | 41634 | 0 | 0 |
T15 | 149625 | 149320 | 0 | 0 |
T30 | 95696 | 95638 | 0 | 0 |
T31 | 113520 | 113515 | 0 | 0 |
T32 | 1768 | 1686 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 69911337 | 69880586 | 0 | 0 |
T1 | 31818 | 31141 | 0 | 0 |
T2 | 61480 | 61421 | 0 | 0 |
T3 | 537215 | 537119 | 0 | 0 |
T4 | 585393 | 585143 | 0 | 0 |
T9 | 115934 | 115928 | 0 | 0 |
T13 | 42071 | 41634 | 0 | 0 |
T15 | 149625 | 149320 | 0 | 0 |
T30 | 95696 | 95638 | 0 | 0 |
T31 | 113520 | 113515 | 0 | 0 |
T32 | 1768 | 1686 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |