Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.91 96.97 59.57 90.53 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 110697130 9477 0 0
late_debug_enable_rd_A 110697130 4747 0 0
late_debug_enable_regwen_rd_A 110697130 3510 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110697130 9477 0 0
T62 365646 33 0 0
T63 9914 13 0 0
T64 227296 3 0 0
T69 7018 398 0 0
T70 72008 4 0 0
T74 88506 99 0 0
T75 10665 301 0 0
T76 8132 17 0 0
T77 16211 314 0 0
T78 127988 68 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110697130 4747 0 0
T63 9914 20 0 0
T64 227296 16 0 0
T70 72008 48 0 0
T74 88506 34 0 0
T77 16211 111 0 0
T79 138425 89 0 0
T80 11511 70 0 0
T91 57328 38 0 0
T104 7276 7 0 0
T110 21898 1 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110697130 3510 0 0
T63 9914 6 0 0
T64 227296 32 0 0
T70 72008 55 0 0
T74 88506 34 0 0
T77 16211 70 0 0
T79 138425 97 0 0
T80 11511 87 0 0
T91 57328 83 0 0
T110 21898 7 0 0
T120 14847 24 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%