Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.91 96.97 59.57 90.53 100.00 87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 86.91 96.97 59.57 90.53 100.00 87.50



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.91 96.97 59.57 90.53 100.00 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.78 95.27 79.03 88.93 67.95 85.17 98.32


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
dap 81.19 98.03 82.55 58.00 92.39 75.00
enable_checker 75.00 75.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
i_tlul_adapter_reg 93.27 99.00 80.90 93.33 93.10 100.00
rv_dm_regs_csr_assert 100.00 100.00
tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 95.24 100.00 85.71 100.00
tlul_assert_device_regs 95.12 100.00 85.71 99.65
tlul_assert_host_sba 94.30 100.00 85.71 97.18
u_dm_top 84.37 88.16 66.84 92.86 73.99 100.00
u_lc_en_sync_copies 100.00 100.00 100.00
u_pm_en_sync 100.00 100.00 100.00 100.00
u_prim_clock_mux2 85.19 100.00 55.56 100.00
u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
u_prim_rst_n_mux2 85.19 100.00 55.56 100.00
u_reg_regs 98.19 98.69 98.71 93.55 100.00 100.00
u_tlul_lc_gate_rom 91.18 99.21 78.57 100.00 90.62 87.50
u_tlul_lc_gate_sba 74.11 89.76 64.29 57.14 71.88 87.50


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm
Line No.TotalCoveredPercent
TOTAL333296.97
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN154100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
ALWAYS3201111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
122 1 1
123 1 1
128 1 1
131 1 1
154 0 1
236 1 1
237 1 1
239 4 4
278 1 1
288 1 1
289 1 1
320 1 1
321 1 1
322 1 1
325 1 1
326 1 1
327 1 1
328 1 1
MISSING_ELSE
331 1 1
332 1 1
333 1 1
334 1 1
MISSING_ELSE
345 1 1
432 1 1
438 1 1
440 1 1
446 1 1
447 1 1
523 1 1
551 1 1


Cond Coverage for Module : rv_dm
TotalCoveredPercent
Conditions472859.57
Logical472859.57
Non-Logical00
Event00

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T6,T2
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT56,T57,T58

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT32,T33,T43
10CoveredT1,T32,T33
11CoveredT32,T33,T43

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T6,T2
10CoveredT2,T10,T7
11CoveredT2,T3,T30

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T6,T2
10CoveredT2,T3,T30
11CoveredT2,T3,T30

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------
-1--2-StatusTests
01CoveredT2,T3,T30
10Not Covered
11Not Covered

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----
-1--2--3--4--5-StatusTests
01111Not Covered
10111Not Covered
11011Not Covered
11101Not Covered
11110Not Covered
11111Not Covered

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T6,T2
10CoveredT34,T35
11CoveredT1,T2,T3

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T6,T2
10CoveredT2,T3,T12
11CoveredT1,T6,T2

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T6,T2
10Not Covered
11CoveredT1,T6,T2

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T6,T2
01CoveredT6,T2,T27
10CoveredT1,T2,T3

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T6,T2
10Not Covered
11CoveredT1,T6,T2

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T6,T2
10CoveredT2,T3,T12
11CoveredT1,T6,T2

Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 98 76 77.55
Total Bits 1140 1032 90.53
Total Bits 0->1 570 516 90.53
Total Bits 1->0 570 516 90.53

Ports 98 76 77.55
Port Bits 1140 1032 90.53
Port Bits 0->1 570 516 90.53
Port Bits 1->0 570 516 90.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T6,T2 Yes T1,T6,T2 INPUT
clk_lc_i No No No INPUT
rst_ni Yes Yes T2,T3,T12 Yes T1,T6,T2 INPUT
rst_lc_ni No No No INPUT
next_dm_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
lc_hw_debug_en_i[3:0] Yes Yes T2,T10,T7 Yes T2,T3,T30 INPUT
lc_dft_en_i[0] No No Yes T3,T30,T5 INPUT
lc_dft_en_i[1] No Yes *T3,*T30,*T5 No INPUT
lc_dft_en_i[2] No No Yes T3,T30,T5 INPUT
lc_dft_en_i[3] No Yes T3,T30,T5 No INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T27,T21,T10 Yes T3,T27,T30 INPUT
otp_dis_rv_dm_late_debug_i[7:0] No No No INPUT
scanmode_i[3:0] No No No INPUT
scan_rst_ni Yes Yes T2,T3,T12 Yes T1,T6,T2 INPUT
ndmreset_req_o Yes Yes T2,T3,T30 Yes T2,T3,T30 OUTPUT
dmactive_o Yes Yes T2,T3,T12 Yes T1,T6,T2 OUTPUT
debug_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
unavailable_i Yes Yes T2,T3,T30 Yes T2,T3,T30 INPUT
regs_tl_d_i.d_ready Yes Yes T1,T2,T3 Yes T1,T6,T2 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T32,T33,T43 Yes T1,T32,T33 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T1,T32,T33 Yes T32,T33,T43 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T32,T44,T25 Yes T32,T44,T25 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T32,T44,T25 Yes T1,T32,T44 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T32,T33,T43 Yes T1,T32,T33 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T32,T44,T25 Yes T6,T32,T44 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T32,T44,T25 Yes T6,T32,T44 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T32,T44,T25 Yes T32,T44,T25 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T1,T32,T33 Yes T6,T32,T33 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T6,T32,T44 Yes T32,T44,T25 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T32,T33,T43 Yes T6,T32,T33 INPUT
regs_tl_d_i.a_valid Yes Yes T32,T33,T43 Yes T32,T33,T43 INPUT
regs_tl_d_o.a_ready Yes Yes T32,T33,T43 Yes T32,T33,T43 OUTPUT
regs_tl_d_o.d_error Yes Yes T62,T63,T64 Yes T62,T63,T64 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] Yes Yes T62,T63,T64 Yes T62,T63,T64 OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T32,*T33,*T43 Yes T32,T33,T43 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T62,T63,T64 Yes T32,T33,T43 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[7:0] Yes Yes T32,T44,T37 Yes T32,T33,T43 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T32,T33,T43 Yes T32,T33,T43 OUTPUT
regs_tl_d_o.d_param[2:0] No No No OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T62,*T63,*T64 Yes T62,T63,T64 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T32,T33,T43 Yes T32,T33,T43 OUTPUT
mem_tl_d_i.d_ready Yes Yes T1,T2,T3 Yes T1,T6,T2 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T6,T4,T18 Yes T6,T2,T4 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T1,T6,T2 Yes T1,T6,T2 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T4,T18,T56 Yes T4,T18,T56 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T4,T18,T56 Yes T4,T18,T56 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T6,T2,T4 Yes T6,T2,T4 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T2,T4,T18 Yes T4,T18,T27 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T4,T18,T27 Yes T4,T18,T27 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T4,T18,T56 Yes T4,T18,T56 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_valid Yes Yes T1,T6,T2 Yes T1,T6,T2 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T6,T2 Yes T1,T6,T2 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T6,T2 Yes T2,T3,T12 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T6,T27,T5 Yes T6,T27,T5 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T6,T2 Yes T1,T6,T2 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[7:0] Yes Yes T2,T3,T18 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_param[2:0] No No No OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T6,*T2 Yes T6,T2,T3 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T1,T6,T2 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.d_ready Yes Yes T2,T3,T12 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T12 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T2,*T3,*T12 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T2,T3,T12 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] No No No OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T2,T3,T12 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
sba_tl_h_o.a_source[7:0] No No No OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T2,T3,T12 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.a_param[2:0] No No No OUTPUT
sba_tl_h_o.a_opcode[0] Yes Yes *T12,*T13,*T14 Yes T12,T13,T14 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T2,T3,T12 Yes T1,T6,T2 OUTPUT
sba_tl_h_o.a_valid Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
sba_tl_h_i.a_ready Yes Yes T1,T2,T3 Yes T1,T6,T2 INPUT
sba_tl_h_i.d_error Yes Yes T12,T44,T25 Yes T12,T18,T25 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T12,T13,T14 Yes T12,T13,T18 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T12,T13,T33 Yes T12,T13,T18 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T12,T13,T14 Yes T12,T13,T14 INPUT
sba_tl_h_i.d_sink Yes Yes T12,T13,T14 Yes T12,T13,T18 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T25,T39,T65 Yes T18,T33,T25 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T12,T25,T21 Yes T18,T43,T25 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T43,T25,T5 Yes T33,T25,T21 INPUT
sba_tl_h_i.d_opcode[2:0] Yes Yes T12,T13,T14 Yes T12,T13,T18 INPUT
sba_tl_h_i.d_valid Yes Yes T12,T13,T14 Yes T12,T13,T14 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T6,T2 Yes T1,T6,T2 INPUT
alert_rx_i[0].ack_p Yes Yes T32,T33,T43 Yes T32,T33,T43 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T6,T2 Yes T1,T6,T2 OUTPUT
alert_tx_o[0].alert_p Yes Yes T32,T33,T43 Yes T32,T33,T43 OUTPUT
jtag_i.tdi Yes Yes T1,T6,T2 Yes T1,T6,T2 INPUT
jtag_i.trst_n Yes Yes T2,T3,T12 Yes T1,T6,T2 INPUT
jtag_i.tms Yes Yes T1,T6,T2 Yes T1,T6,T2 INPUT
jtag_i.tck Yes Yes T1,T6,T2 Yes T1,T6,T2 INPUT
jtag_o.tdo_oe Yes Yes T1,T6,T2 Yes T1,T6,T2 OUTPUT
jtag_o.tdo Yes Yes T1,T6,T2 Yes T1,T6,T2 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_dm
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 320 7 7 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 320 if ((!rst_ni)) -2-: 325 if ((ndmreset_req && (!ndmreset_pending_q))) -3-: 327 if ((ndmreset_ack && ndmreset_pending_q)) -4-: 331 if ((ndmreset_pending_q && lc_rst_asserted)) -5-: 333 if ((ndmreset_ack && lc_rst_pending_q))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T6,T2
0 1 - - - Covered T2,T3,T30
0 0 1 - - Covered T2,T3,T30
0 0 0 - - Covered T1,T6,T2
0 - - 1 - Covered T2,T3,T30
0 - - 0 1 Covered T2,T3,T30
0 - - 0 0 Covered T1,T6,T2


Assert Coverage for Module : rv_dm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 14 87.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 14 87.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 49647471 49607609 0 0
DmactiveOKnown_A 49647471 49607609 0 0
FpvSecCmRegWeOnehotCheck_A 49647471 80 0 0
FpvSecCmRomTlLcGateFsm_A 49647471 0 0 0
FpvSecCmSbaTlLcGateFsm_A 49647471 0 0 0
JtagRspOTdoKnown_A 2722269 2722137 0 0
JtagRspOTdoOeKnown_A 2722269 2722137 0 0
NdmresetOKnown_A 49647471 49607609 0 0
RvDmLcEnDebugVal_A 49647471 49607609 0 0
TlMemAReadyKnown_A 49647471 49607609 0 0
TlMemDValidKnown_A 49647471 49607609 0 0
TlRegsAReadyKnown_A 49647471 49607609 0 0
TlRegsDValidKnown_A 49647471 49607609 0 0
TlSbaAValidKnown_A 49647471 49607609 0 0
TlSbaDReadyKnown_A 49647471 49607609 0 0
paramCheckNrHarts 225 225 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 80 0 0
T5 66765 0 0 0
T10 630244 0 0 0
T21 101497 0 0 0
T30 575524 0 0 0
T31 482838 0 0 0
T34 1838 0 0 0
T36 3476 0 0 0
T41 493116 0 0 0
T56 10205 10 0 0
T57 0 20 0 0
T58 0 20 0 0
T66 0 20 0 0
T67 0 10 0 0
T68 13262 0 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2722269 2722137 0 0
T1 3112 3112 0 0
T2 29564 29562 0 0
T3 21308 21305 0 0
T4 1568 1568 0 0
T6 462 462 0 0
T12 9807 9807 0 0
T13 8610 8610 0 0
T18 4925 4925 0 0
T32 196 196 0 0
T33 225 225 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2722269 2722137 0 0
T1 3112 3112 0 0
T2 29564 29562 0 0
T3 21308 21305 0 0
T4 1568 1568 0 0
T6 462 462 0 0
T12 9807 9807 0 0
T13 8610 8610 0 0
T18 4925 4925 0 0
T32 196 196 0 0
T33 225 225 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 49647471 49607609 0 0
T1 49234 49178 0 0
T2 90244 89921 0 0
T3 495591 495010 0 0
T4 9278 9221 0 0
T6 1792 1729 0 0
T12 121624 121449 0 0
T13 160291 160211 0 0
T18 25863 25807 0 0
T32 3255 3189 0 0
T33 2524 2434 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 225 225 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%