Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.91	96.97	59.57	90.53		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	49647471	7142618	0	0
MemTLResponseWithoutDebugIsError_A	49647471	2	0	0
NdmResetAckNeedsDebug_A	49647471	0	0	0
SbaTLRequestNeedsDebug_A	49647471	15062	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	7142618	0	0
T1	49234	15802	0	0
T2	90244	27182	0	0
T3	495591	164671	0	0
T4	9278	6465	0	0
T5	0	29583	0	0
T6	1792	0	0	0
T12	121624	0	0	0
T13	160291	0	0	0
T18	25863	24280	0	0
T19	0	22782	0	0
T27	0	375380	0	0
T30	0	148533	0	0
T31	0	189174	0	0
T32	3255	0	0	0
T33	2524	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	2	0	0
T7	800215	0	0	0
T10	630244	0	0	0
T21	101497	0	0	0
T28	750131	0	0	0
T34	1838	1	0	0
T35	0	1	0	0
T36	3476	0	0	0
T37	2209	0	0	0
T38	278422	0	0	0
T39	797270	0	0	0
T40	2181	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	15062	0	0
T4	9278	0	0	0
T12	121624	48	0	0
T13	160291	36	0	0
T14	121665	112	0	0
T18	25863	0	0	0
T19	25871	0	0	0
T25	117863	169	0	0
T26	0	56	0	0
T28	0	12	0	0
T33	2524	0	0	0
T38	0	59	0	0
T39	0	19	0	0
T41	0	101	0	0
T42	0	15	0	0
T43	3228	0	0	0
T44	4766	0	0	0