Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	227465	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	614479	1		T3	2		T4	15		T26	11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	534680	1		T3	1		T4	2		T26	6
values[0x0]	151376	1		T2	2		T3	4		T4	23
values[0x1]	155888	1		T2	2		T3	4		T4	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173215	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	668729	1		T3	3		T4	23		T26	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3079	1		T32	2		T7	2		T67	119
valid_sources[0x01]	3690	1		T142	1		T23	1		T143	1
valid_sources[0x02]	3600	1		T63	332		T67	128		T66	1
valid_sources[0x03]	3361	1		T27	1		T67	116		T66	2
valid_sources[0x04]	3183	1		T26	1		T34	1		T143	1
valid_sources[0x05]	2799	1		T27	1		T18	1		T15	1
valid_sources[0x06]	2792	1		T144	3		T67	119		T66	1
valid_sources[0x07]	2737	1		T5	4		T67	99		T65	14
valid_sources[0x08]	3212	1		T34	1		T67	121		T66	2
valid_sources[0x09]	3324	1		T89	2		T67	108		T66	2
valid_sources[0x0a]	2797	1		T67	123		T66	1		T64	26
valid_sources[0x0b]	3411	1		T18	1		T67	124		T65	24
valid_sources[0x0c]	3324	1		T27	1		T145	2		T67	100
valid_sources[0x0d]	3194	1		T11	1		T144	1		T67	110
valid_sources[0x0e]	3678	1		T16	2		T63	275		T67	102
valid_sources[0x0f]	3423	1		T11	1		T15	1		T67	101
valid_sources[0x10]	3046	1		T67	110		T66	1		T64	9
valid_sources[0x11]	2935	1		T19	2		T23	1		T143	1
valid_sources[0x12]	3323	1		T67	107		T65	16		T72	1
valid_sources[0x13]	3077	1		T142	1		T15	1		T67	111
valid_sources[0x14]	2990	1		T37	1		T146	2		T143	1
valid_sources[0x15]	2915	1		T17	1		T7	1		T142	2
valid_sources[0x16]	6441	1		T11	1		T142	1		T67	120
valid_sources[0x17]	3702	1		T143	1		T67	106		T64	2
valid_sources[0x18]	2810	1		T147	1		T143	1		T67	110
valid_sources[0x19]	2925	1		T34	1		T67	118		T66	1
valid_sources[0x1a]	2821	1		T148	2		T67	105		T66	1
valid_sources[0x1b]	2927	1		T26	1		T32	2		T5	3
valid_sources[0x1c]	3526	1		T11	1		T23	2		T67	100
valid_sources[0x1d]	3373	1		T148	5		T67	112		T66	1
valid_sources[0x1e]	2599	1		T5	1		T67	104		T65	19
valid_sources[0x1f]	3383	1		T53	1		T67	91		T66	1
valid_sources[0x20]	3234	1		T11	1		T67	122		T65	29
valid_sources[0x21]	3129	1		T56	1		T67	97		T66	1
valid_sources[0x22]	2807	1		T15	1		T149	1		T67	103
valid_sources[0x23]	3156	1		T23	1		T63	162		T67	101
valid_sources[0x24]	3683	1		T31	4		T19	1		T67	130
valid_sources[0x25]	3049	1		T67	115		T66	1		T65	29
valid_sources[0x26]	3109	1		T11	1		T67	98		T66	2
valid_sources[0x27]	3278	1		T67	103		T66	2		T64	420
valid_sources[0x28]	3364	1		T4	58		T7	3		T146	1
valid_sources[0x29]	2817	1		T27	1		T52	11		T150	3
valid_sources[0x2a]	3140	1		T26	1		T151	2		T63	83
valid_sources[0x2b]	2970	1		T152	2		T23	1		T67	143
valid_sources[0x2c]	3248	1		T18	1		T23	1		T67	113
valid_sources[0x2d]	3247	1		T67	101		T66	1		T65	14
valid_sources[0x2e]	3346	1		T153	2		T148	2		T67	115
valid_sources[0x2f]	3190	1		T27	1		T7	1		T23	1
valid_sources[0x30]	2919	1		T15	2		T67	117		T64	2
valid_sources[0x31]	2880	1		T15	1		T149	1		T63	1
valid_sources[0x32]	3081	1		T142	1		T23	1		T67	106
valid_sources[0x33]	3102	1		T142	1		T67	104		T66	2
valid_sources[0x34]	3105	1		T23	3		T67	104		T66	2
valid_sources[0x35]	3284	1		T16	3		T23	2		T67	128
valid_sources[0x36]	3296	1		T142	3		T67	96		T66	2
valid_sources[0x37]	3020	1		T34	1		T154	5		T15	3
valid_sources[0x38]	3086	1		T27	1		T147	1		T67	98
valid_sources[0x39]	3175	1		T26	1		T7	3		T155	8
valid_sources[0x3a]	3011	1		T67	115		T64	19		T65	14
valid_sources[0x3b]	3217	1		T27	1		T148	1		T67	103
valid_sources[0x3c]	3068	1		T34	1		T144	1		T148	2
valid_sources[0x3d]	6393	1		T67	106		T66	2		T65	13
valid_sources[0x3e]	3326	1		T26	1		T27	1		T63	99
valid_sources[0x3f]	3238	1		T56	1		T67	117		T66	1
valid_sources[0x40]	3180	1		T67	105		T66	2		T64	11
valid_sources[0x41]	3480	1		T26	1		T7	1		T15	1
valid_sources[0x42]	3075	1		T32	1		T27	1		T63	40
valid_sources[0x43]	3208	1		T19	2		T67	108		T66	1
valid_sources[0x44]	3444	1		T39	1		T156	1		T7	1
valid_sources[0x45]	3329	1		T149	2		T63	44		T67	118
valid_sources[0x46]	2880	1		T27	1		T149	1		T67	91
valid_sources[0x47]	2751	1		T67	88		T66	3		T64	13
valid_sources[0x48]	3218	1		T67	106		T66	3		T65	27
valid_sources[0x49]	3359	1		T27	1		T147	1		T67	104
valid_sources[0x4a]	3193	1		T22	1		T67	95		T66	1
valid_sources[0x4b]	2818	1		T34	1		T67	100		T66	1
valid_sources[0x4c]	2791	1		T7	1		T23	2		T67	99
valid_sources[0x4d]	3391	1		T15	1		T67	103		T66	1
valid_sources[0x4e]	5714	1		T11	1		T67	108		T65	25
valid_sources[0x4f]	2682	1		T67	112		T65	16		T79	37
valid_sources[0x50]	2848	1		T15	2		T23	2		T67	93
valid_sources[0x51]	3396	1		T31	6		T88	1		T142	3
valid_sources[0x52]	3212	1		T144	3		T56	1		T67	109
valid_sources[0x53]	3097	1		T3	1		T53	2		T67	123
valid_sources[0x54]	3072	1		T13	1		T7	1		T15	1
valid_sources[0x55]	2844	1		T32	2		T67	110		T65	25
valid_sources[0x56]	3496	1		T142	1		T53	1		T63	275
valid_sources[0x57]	3469	1		T18	1		T67	116		T66	2
valid_sources[0x58]	3319	1		T148	2		T67	109		T66	1
valid_sources[0x59]	3303	1		T26	1		T15	1		T53	1
valid_sources[0x5a]	2820	1		T5	5		T143	1		T63	55
valid_sources[0x5b]	2664	1		T34	2		T5	1		T142	1
valid_sources[0x5c]	3628	1		T26	1		T156	1		T146	4
valid_sources[0x5d]	3642	1		T26	1		T34	1		T23	2
valid_sources[0x5e]	3022	1		T19	1		T67	122		T66	3
valid_sources[0x5f]	2942	1		T11	1		T15	1		T67	128
valid_sources[0x60]	2927	1		T26	2		T157	7		T22	1
valid_sources[0x61]	3052	1		T19	1		T146	5		T67	101
valid_sources[0x62]	3176	1		T146	2		T148	2		T63	51
valid_sources[0x63]	2929	1		T158	1		T159	12		T67	100
valid_sources[0x64]	2958	1		T26	1		T67	100		T66	2
valid_sources[0x65]	3186	1		T53	3		T67	121		T66	3
valid_sources[0x66]	6237	1		T27	2		T152	3		T151	1
valid_sources[0x67]	2870	1		T3	1		T23	2		T67	112
valid_sources[0x68]	3115	1		T23	1		T148	2		T67	116
valid_sources[0x69]	3121	1		T63	128		T67	105		T66	3
valid_sources[0x6a]	3152	1		T18	1		T23	1		T67	111
valid_sources[0x6b]	3252	1		T7	6		T63	6		T67	110
valid_sources[0x6c]	3376	1		T17	1		T67	101		T65	19
valid_sources[0x6d]	2683	1		T15	1		T67	115		T66	3
valid_sources[0x6e]	2917	1		T7	4		T15	1		T143	1
valid_sources[0x6f]	2905	1		T27	1		T67	118		T66	4
valid_sources[0x70]	2994	1		T67	103		T65	20		T79	21
valid_sources[0x71]	3489	1		T67	80		T66	2		T64	279
valid_sources[0x72]	3099	1		T3	2		T26	1		T67	93
valid_sources[0x73]	3129	1		T160	10		T16	2		T143	1
valid_sources[0x74]	3390	1		T26	1		T11	1		T142	1
valid_sources[0x75]	2925	1		T67	108		T65	23		T79	40
valid_sources[0x76]	2797	1		T23	1		T67	132		T65	37
valid_sources[0x77]	3590	1		T63	632		T67	130		T66	3
valid_sources[0x78]	3240	1		T67	114		T65	12		T78	237
valid_sources[0x79]	4143	1		T34	1		T19	1		T18	1
valid_sources[0x7a]	3903	1		T88	1		T143	1		T63	827
valid_sources[0x7b]	3092	1		T19	1		T23	1		T67	114
valid_sources[0x7c]	3321	1		T67	124		T66	1		T64	2
valid_sources[0x7d]	2975	1		T67	113		T66	1		T65	18
valid_sources[0x7e]	3290	1		T142	1		T151	2		T63	275
valid_sources[0x7f]	3546	1		T7	3		T148	1		T67	115
valid_sources[0x80]	2991	1		T27	1		T5	1		T146	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

315972

1

T4

2

T26

4

T32

1

values[0x0]

all_enables

biggest_size

149399

1

T3

2

T4

9

T26

5

values[0x1]

all_enables

biggest_size

149108

1

T4

4

T26

2

T32

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5025	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16277	1		T36	1		T38	3		T41	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8854	1		T63	67		T67	284		T66	139
values[0x0]	6123	1		T36	6		T38	9		T41	8
values[0x1]	6325	1		T36	2		T38	7		T41	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3901	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17401	1		T36	2		T38	4		T41	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	81	1		T63	2		T67	8		T66	5
valid_sources[0x01]	79	1		T67	1		T66	2		T64	2
valid_sources[0x02]	159	1		T63	1		T67	1		T66	3
valid_sources[0x03]	72	1		T63	1		T67	1		T66	1
valid_sources[0x04]	40	1		T67	1		T66	1		T90	2
valid_sources[0x05]	66	1		T161	1		T67	3		T66	2
valid_sources[0x06]	57	1		T73	1		T66	3		T64	1
valid_sources[0x07]	117	1		T44	9		T66	2		T64	1
valid_sources[0x08]	59	1		T162	1		T163	1		T164	1
valid_sources[0x09]	75	1		T63	1		T66	4		T96	5
valid_sources[0x0a]	88	1		T165	2		T166	2		T63	1
valid_sources[0x0b]	50	1		T164	1		T67	1		T66	2
valid_sources[0x0c]	69	1		T66	3		T64	1		T80	3
valid_sources[0x0d]	62	1		T167	4		T94	7		T96	6
valid_sources[0x0e]	135	1		T130	1		T72	44		T96	2
valid_sources[0x0f]	85	1		T168	2		T169	2		T66	3
valid_sources[0x10]	50	1		T66	3		T64	1		T96	3
valid_sources[0x11]	66	1		T63	1		T67	1		T66	3
valid_sources[0x12]	102	1		T170	1		T63	1		T66	2
valid_sources[0x13]	44	1		T171	3		T162	1		T66	1
valid_sources[0x14]	70	1		T67	4		T66	1		T96	6
valid_sources[0x15]	133	1		T130	1		T63	1		T67	2
valid_sources[0x16]	112	1		T38	3		T67	9		T66	1
valid_sources[0x17]	106	1		T66	1		T64	2		T95	3
valid_sources[0x18]	57	1		T68	1		T63	3		T67	4
valid_sources[0x19]	47	1		T161	3		T164	1		T63	3
valid_sources[0x1a]	46	1		T68	1		T167	1		T65	1
valid_sources[0x1b]	55	1		T66	1		T93	1		T96	1
valid_sources[0x1c]	105	1		T172	1		T66	2		T64	2
valid_sources[0x1d]	74	1		T68	3		T161	1		T63	4
valid_sources[0x1e]	75	1		T38	1		T173	2		T130	1
valid_sources[0x1f]	56	1		T66	2		T90	1		T80	1
valid_sources[0x20]	147	1		T77	2		T174	1		T67	2
valid_sources[0x21]	136	1		T66	3		T64	2		T65	1
valid_sources[0x22]	53	1		T66	2		T64	1		T93	2
valid_sources[0x23]	62	1		T41	1		T170	4		T66	1
valid_sources[0x24]	73	1		T41	1		T175	7		T67	5
valid_sources[0x25]	65	1		T66	1		T96	1		T97	1
valid_sources[0x26]	49	1		T38	2		T66	2		T96	2
valid_sources[0x27]	81	1		T64	2		T93	1		T96	5
valid_sources[0x28]	118	1		T63	2		T67	8		T66	3
valid_sources[0x29]	53	1		T41	1		T66	1		T79	3
valid_sources[0x2a]	108	1		T124	18		T176	5		T67	5
valid_sources[0x2b]	44	1		T90	1		T93	1		T96	6
valid_sources[0x2c]	132	1		T172	3		T63	1		T66	2
valid_sources[0x2d]	74	1		T162	1		T177	1		T172	3
valid_sources[0x2e]	58	1		T178	9		T66	6		T96	2
valid_sources[0x2f]	81	1		T161	1		T162	1		T63	1
valid_sources[0x30]	68	1		T179	1		T63	1		T67	8
valid_sources[0x31]	80	1		T168	1		T162	1		T63	2
valid_sources[0x32]	47	1		T63	5		T66	2		T64	1
valid_sources[0x33]	116	1		T180	16		T67	6		T66	3
valid_sources[0x34]	62	1		T67	1		T79	5		T90	1
valid_sources[0x35]	89	1		T63	3		T67	1		T66	1
valid_sources[0x36]	60	1		T67	1		T66	4		T64	1
valid_sources[0x37]	55	1		T168	1		T181	6		T66	3
valid_sources[0x38]	65	1		T165	4		T66	2		T64	1
valid_sources[0x39]	106	1		T182	17		T63	3		T66	3
valid_sources[0x3a]	53	1		T67	1		T66	2		T64	2
valid_sources[0x3b]	91	1		T66	3		T64	2		T65	1
valid_sources[0x3c]	69	1		T63	1		T67	1		T66	2
valid_sources[0x3d]	72	1		T165	1		T66	3		T65	1
valid_sources[0x3e]	45	1		T63	1		T96	2		T97	2
valid_sources[0x3f]	50	1		T165	1		T177	1		T66	2
valid_sources[0x40]	80	1		T67	1		T66	1		T65	1
valid_sources[0x41]	71	1		T67	1		T66	2		T93	1
valid_sources[0x42]	69	1		T66	1		T94	1		T96	3
valid_sources[0x43]	48	1		T167	1		T164	1		T64	1
valid_sources[0x44]	56	1		T38	2		T66	2		T64	2
valid_sources[0x45]	114	1		T170	1		T65	1		T79	6
valid_sources[0x46]	48	1		T63	2		T66	3		T79	1
valid_sources[0x47]	107	1		T169	3		T63	3		T67	1
valid_sources[0x48]	91	1		T63	2		T66	2		T64	2
valid_sources[0x49]	99	1		T66	3		T64	1		T65	1
valid_sources[0x4a]	61	1		T130	2		T67	4		T66	3
valid_sources[0x4b]	71	1		T168	1		T183	2		T63	1
valid_sources[0x4c]	85	1		T66	2		T92	1		T93	1
valid_sources[0x4d]	101	1		T63	1		T66	3		T64	2
valid_sources[0x4e]	75	1		T66	2		T64	1		T65	1
valid_sources[0x4f]	85	1		T165	1		T162	1		T67	1
valid_sources[0x50]	98	1		T179	3		T171	2		T166	2
valid_sources[0x51]	94	1		T184	8		T63	1		T67	1
valid_sources[0x52]	91	1		T63	3		T67	1		T90	1
valid_sources[0x53]	94	1		T66	3		T64	1		T72	38
valid_sources[0x54]	63	1		T165	1		T170	2		T66	1
valid_sources[0x55]	90	1		T67	1		T66	2		T65	2
valid_sources[0x56]	166	1		T185	1		T66	3		T90	3
valid_sources[0x57]	71	1		T67	1		T66	2		T64	3
valid_sources[0x58]	49	1		T185	1		T67	4		T64	1
valid_sources[0x59]	71	1		T38	1		T173	1		T96	4
valid_sources[0x5a]	49	1		T186	1		T66	4		T96	2
valid_sources[0x5b]	67	1		T63	1		T66	1		T65	1
valid_sources[0x5c]	81	1		T63	1		T67	1		T66	4
valid_sources[0x5d]	79	1		T63	1		T66	1		T79	1
valid_sources[0x5e]	276	1		T63	4		T67	9		T66	2
valid_sources[0x5f]	67	1		T168	3		T63	2		T66	3
valid_sources[0x60]	241	1		T161	1		T177	3		T66	2
valid_sources[0x61]	45	1		T63	1		T66	1		T93	1
valid_sources[0x62]	39	1		T170	2		T67	1		T66	1
valid_sources[0x63]	60	1		T73	1		T172	2		T67	1
valid_sources[0x64]	60	1		T63	1		T66	1		T64	2
valid_sources[0x65]	100	1		T63	2		T64	2		T94	1
valid_sources[0x66]	54	1		T186	1		T67	3		T96	5
valid_sources[0x67]	70	1		T77	1		T66	1		T65	2
valid_sources[0x68]	72	1		T63	1		T66	2		T65	1
valid_sources[0x69]	112	1		T76	12		T66	3		T64	1
valid_sources[0x6a]	80	1		T67	1		T66	1		T64	1
valid_sources[0x6b]	84	1		T87	14		T174	1		T63	1
valid_sources[0x6c]	130	1		T63	1		T67	7		T66	2
valid_sources[0x6d]	104	1		T66	1		T93	1		T96	1
valid_sources[0x6e]	298	1		T38	1		T73	1		T63	2
valid_sources[0x6f]	130	1		T63	1		T66	1		T64	1
valid_sources[0x70]	106	1		T172	2		T63	2		T67	2
valid_sources[0x71]	77	1		T66	1		T96	2		T82	2
valid_sources[0x72]	78	1		T183	2		T66	1		T90	1
valid_sources[0x73]	96	1		T66	1		T65	1		T94	22
valid_sources[0x74]	44	1		T38	1		T172	1		T67	2
valid_sources[0x75]	58	1		T67	1		T66	3		T90	1
valid_sources[0x76]	86	1		T176	4		T67	2		T93	1
valid_sources[0x77]	69	1		T67	2		T66	3		T93	2
valid_sources[0x78]	148	1		T170	1		T67	5		T66	2
valid_sources[0x79]	71	1		T170	1		T63	3		T66	4
valid_sources[0x7a]	96	1		T161	2		T67	4		T64	3
valid_sources[0x7b]	76	1		T67	1		T66	3		T65	1
valid_sources[0x7c]	65	1		T172	1		T66	5		T64	2
valid_sources[0x7d]	100	1		T165	1		T67	3		T66	1
valid_sources[0x7e]	72	1		T179	3		T65	1		T93	2
valid_sources[0x7f]	64	1		T162	1		T67	1		T66	3
valid_sources[0x80]	48	1		T67	2		T66	3		T78	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5922

1

T63

28

T67

142

T66

128

values[0x0]

all_enables

biggest_size

5268

1

T36

1

T38

1

T41

4

values[0x1]

all_enables

biggest_size

5087

1

T38

2

T41

1

T44

1