Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 263500 1 T2 4 T3 7 T4 43
full_word 615876 1 T3 2 T4 15 T26 11



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 879056 1 T2 4 T3 9 T4 58
auto[TlIntgErrCmd] 99 1 T63 8 T65 4 T78 2
auto[TlIntgErrData] 112 1 T63 4 T65 3 T78 4
auto[TlIntgErrBoth] 109 1 T63 8 T65 3 T78 4



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 536384 1 T3 1 T4 2 T26 6
auto[1] 342992 1 T2 4 T3 8 T4 56



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 220100 1 T3 1 T26 2 T27 1
auto[TlIntgErrNone] partial auto[1] 43112 1 T2 4 T3 6 T4 43
auto[TlIntgErrNone] full_word auto[0] 316149 1 T4 2 T26 4 T32 1
auto[TlIntgErrNone] full_word auto[1] 299695 1 T3 2 T4 13 T26 7
auto[TlIntgErrCmd] partial auto[0] 32 1 T63 2 T65 2 T78 2
auto[TlIntgErrCmd] partial auto[1] 53 1 T63 6 T65 2 T79 1
auto[TlIntgErrCmd] full_word auto[0] 4 1 T81 1 T138 1 T139 1
auto[TlIntgErrCmd] full_word auto[1] 10 1 T79 1 T82 1 T84 1
auto[TlIntgErrData] partial auto[0] 42 1 T65 1 T78 2 T79 1
auto[TlIntgErrData] partial auto[1] 64 1 T63 4 T65 1 T78 2
auto[TlIntgErrData] full_word auto[0] 2 1 T135 1 T139 1 - -
auto[TlIntgErrData] full_word auto[1] 4 1 T65 1 T140 1 T139 2
auto[TlIntgErrBoth] partial auto[0] 50 1 T63 4 T65 2 T78 2
auto[TlIntgErrBoth] partial auto[1] 47 1 T63 3 T65 1 T78 2
auto[TlIntgErrBoth] full_word auto[0] 5 1 T63 1 T79 1 T82 1
auto[TlIntgErrBoth] full_word auto[1] 7 1 T80 1 T81 1 T141 1

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