Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	263500	1		T2	4		T3	7		T4	43
full_word	615876	1		T3	2		T4	15		T26	11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	879056	1		T2	4		T3	9		T4	58
auto[TlIntgErrCmd]	99	1		T63	8		T65	4		T78	2
auto[TlIntgErrData]	112	1		T63	4		T65	3		T78	4
auto[TlIntgErrBoth]	109	1		T63	8		T65	3		T78	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	536384	1		T3	1		T4	2		T26	6
auto[1]	342992	1		T2	4		T3	8		T4	56

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	220100	1		T3	1		T26	2		T27	1
auto[TlIntgErrNone]	partial	auto[1]	43112	1		T2	4		T3	6		T4	43
auto[TlIntgErrNone]	full_word	auto[0]	316149	1		T4	2		T26	4		T32	1
auto[TlIntgErrNone]	full_word	auto[1]	299695	1		T3	2		T4	13		T26	7
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T63	2		T65	2		T78	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T63	6		T65	2		T79	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T81	1		T138	1		T139	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T79	1		T82	1		T84	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T65	1		T78	2		T79	1
auto[TlIntgErrData]	partial	auto[1]	64	1		T63	4		T65	1		T78	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T135	1		T139	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T65	1		T140	1		T139	2
auto[TlIntgErrBoth]	partial	auto[0]	50	1		T63	4		T65	2		T78	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T63	3		T65	1		T78	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T63	1		T79	1		T82	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T80	1		T81	1		T141	1