Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.91 96.97 59.57 90.53 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 120234666 12088 0 0
late_debug_enable_rd_A 120234666 888 0 0
late_debug_enable_regwen_rd_A 120234666 1477 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 120234666 12088 0 0
T63 98321 4 0 0
T64 19291 43 0 0
T65 192297 3 0 0
T66 20287 755 0 0
T72 51725 51 0 0
T78 51829 1 0 0
T79 172905 3 0 0
T80 173178 5 0 0
T81 268962 3 0 0
T82 159739 5 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 120234666 888 0 0
T64 19291 46 0 0
T65 192297 29 0 0
T78 51829 32 0 0
T82 159739 92 0 0
T90 50178 37 0 0
T97 40494 6 0 0
T125 20717 77 0 0
T126 9290 3 0 0
T127 10624 3 0 0
T128 27776 62 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 120234666 1477 0 0
T64 19291 43 0 0
T65 192297 40 0 0
T78 51829 46 0 0
T82 159739 93 0 0
T90 50178 16 0 0
T97 40494 33 0 0
T125 20717 38 0 0
T126 9290 6 0 0
T128 27776 49 0 0
T129 223585 49 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%