Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.91	96.97	59.57	90.53		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	53340480	6630041	0	0
MemTLResponseWithoutDebugIsError_A	53340480	20	0	0
NdmResetAckNeedsDebug_A	53340480	0	0	0
SbaTLRequestNeedsDebug_A	53340480	14651	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53340480	6630041	0	0
T2	266423	95905	0	0
T3	338553	169035	0	0
T4	245207	124737	0	0
T8	73947	0	0	0
T9	32503	0	0	0
T10	18338	0	0	0
T24	236973	0	0	0
T26	0	73984	0	0
T27	0	339694	0	0
T31	0	173537	0	0
T32	0	59470	0	0
T33	0	5759	0	0
T34	0	53980	0	0
T35	0	34757	0	0
T36	13397	0	0	0
T37	1537	0	0	0
T38	6047	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53340480	20	0	0
T24	236973	0	0	0
T26	220886	0	0	0
T37	1537	4	0	0
T38	6047	0	0	0
T39	0	16	0	0
T40	324537	0	0	0
T41	8488	0	0	0
T42	38302	0	0	0
T43	11294	0	0	0
T44	7090	0	0	0
T45	178514	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53340480	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53340480	14651	0	0
T4	245207	0	0	0
T8	73947	33	0	0
T9	32503	42	0	0
T10	18338	12	0	0
T24	236973	8	0	0
T25	0	16	0	0
T28	0	302	0	0
T36	13397	0	0	0
T37	1537	0	0	0
T38	6047	0	0	0
T40	324537	80	0	0
T41	8488	0	0	0
T45	0	68	0	0
T46	0	40	0	0
T47	0	75	0	0