Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7957374 |
7956078 |
0 |
0 |
selKnown1 |
58810063 |
58808759 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7957374 |
7956078 |
0 |
0 |
T1 |
6685 |
6681 |
0 |
0 |
T2 |
19395 |
19391 |
0 |
0 |
T3 |
41778 |
41774 |
0 |
0 |
T4 |
79446 |
79442 |
0 |
0 |
T8 |
10177 |
10173 |
0 |
0 |
T9 |
12516 |
12512 |
0 |
0 |
T10 |
24665 |
24661 |
0 |
0 |
T24 |
21162 |
21158 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
10 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T36 |
270 |
266 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
163 |
320 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58810063 |
58808759 |
0 |
0 |
T1 |
116398 |
116396 |
0 |
0 |
T2 |
276125 |
276121 |
0 |
0 |
T3 |
359416 |
359412 |
0 |
0 |
T4 |
284936 |
284932 |
0 |
0 |
T8 |
79036 |
79032 |
0 |
0 |
T9 |
38762 |
38758 |
0 |
0 |
T10 |
30674 |
30670 |
0 |
0 |
T24 |
247559 |
247555 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
10 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T36 |
13533 |
13529 |
0 |
0 |
T37 |
1539 |
1536 |
0 |
0 |
T38 |
163 |
160 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2487114 |
2486896 |
0 |
0 |
selKnown1 |
53340480 |
53340258 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2487114 |
2486896 |
0 |
0 |
T1 |
3332 |
3331 |
0 |
0 |
T2 |
9692 |
9691 |
0 |
0 |
T3 |
20855 |
20854 |
0 |
0 |
T4 |
39717 |
39716 |
0 |
0 |
T8 |
5087 |
5086 |
0 |
0 |
T9 |
6257 |
6256 |
0 |
0 |
T10 |
12328 |
12327 |
0 |
0 |
T24 |
10576 |
10575 |
0 |
0 |
T36 |
134 |
133 |
0 |
0 |
T38 |
161 |
160 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
53340480 |
53340258 |
0 |
0 |
T1 |
113066 |
113065 |
0 |
0 |
T2 |
266423 |
266422 |
0 |
0 |
T3 |
338553 |
338552 |
0 |
0 |
T4 |
245207 |
245206 |
0 |
0 |
T8 |
73947 |
73946 |
0 |
0 |
T9 |
32503 |
32502 |
0 |
0 |
T10 |
18338 |
18337 |
0 |
0 |
T24 |
236973 |
236972 |
0 |
0 |
T36 |
13397 |
13396 |
0 |
0 |
T37 |
1537 |
1536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
741 |
523 |
0 |
0 |
T1 |
10 |
9 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
30 |
29 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
600 |
378 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T28 |
0 |
5 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5467664 |
5467232 |
0 |
0 |
selKnown1 |
5467467 |
5467039 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5467664 |
5467232 |
0 |
0 |
T1 |
3333 |
3332 |
0 |
0 |
T2 |
9692 |
9691 |
0 |
0 |
T3 |
20855 |
20854 |
0 |
0 |
T4 |
39717 |
39716 |
0 |
0 |
T8 |
5088 |
5087 |
0 |
0 |
T9 |
6257 |
6256 |
0 |
0 |
T10 |
12329 |
12328 |
0 |
0 |
T24 |
10576 |
10575 |
0 |
0 |
T36 |
134 |
133 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
0 |
160 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5467467 |
5467039 |
0 |
0 |
T1 |
3332 |
3331 |
0 |
0 |
T2 |
9692 |
9691 |
0 |
0 |
T3 |
20855 |
20854 |
0 |
0 |
T4 |
39717 |
39716 |
0 |
0 |
T8 |
5087 |
5086 |
0 |
0 |
T9 |
6257 |
6256 |
0 |
0 |
T10 |
12328 |
12327 |
0 |
0 |
T24 |
10576 |
10575 |
0 |
0 |
T36 |
134 |
133 |
0 |
0 |
T38 |
161 |
160 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1855 |
1427 |
0 |
0 |
selKnown1 |
1516 |
1084 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1855 |
1427 |
0 |
0 |
T1 |
10 |
9 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
38 |
37 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1516 |
1084 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
4 |
3 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T28 |
0 |
5 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |