SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.91 | 96.97 | 59.57 | 90.53 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.91 | 96.97 | 59.57 | 90.53 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.91 | 96.97 | 59.57 | 90.53 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.91 | 96.97 | 59.57 | 90.53 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1332 | 1332 | 0 | 0 |
OutputsKnown_A | 320042880 | 319805334 | 0 | 0 |
gen_flops.OutputDelay_A | 160021440 | 159897267 | 0 | 1998 |
gen_no_flops.OutputDelay_A | 160021440 | 159902667 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1332 | 1332 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T10 | 6 | 6 | 0 | 0 |
T24 | 6 | 6 | 0 | 0 |
T36 | 6 | 6 | 0 | 0 |
T37 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 320042880 | 319805334 | 0 | 0 |
T1 | 678396 | 678042 | 0 | 0 |
T2 | 1598538 | 1596666 | 0 | 0 |
T3 | 2031318 | 2029740 | 0 | 0 |
T4 | 1471242 | 1468956 | 0 | 0 |
T8 | 443682 | 443316 | 0 | 0 |
T9 | 195018 | 194718 | 0 | 0 |
T10 | 110028 | 108336 | 0 | 0 |
T24 | 1421838 | 1419684 | 0 | 0 |
T36 | 80382 | 80004 | 0 | 0 |
T37 | 9222 | 8706 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 160021440 | 159897267 | 0 | 1998 |
T1 | 339198 | 339012 | 0 | 9 |
T2 | 799269 | 798288 | 0 | 9 |
T3 | 1015659 | 1014834 | 0 | 9 |
T4 | 735621 | 734424 | 0 | 9 |
T8 | 221841 | 221649 | 0 | 9 |
T9 | 97509 | 97350 | 0 | 9 |
T10 | 55014 | 54132 | 0 | 9 |
T24 | 710919 | 709797 | 0 | 9 |
T36 | 40191 | 39993 | 0 | 9 |
T37 | 4611 | 4344 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 160021440 | 159902667 | 0 | 0 |
T1 | 339198 | 339021 | 0 | 0 |
T2 | 799269 | 798333 | 0 | 0 |
T3 | 1015659 | 1014870 | 0 | 0 |
T4 | 735621 | 734478 | 0 | 0 |
T8 | 221841 | 221658 | 0 | 0 |
T9 | 97509 | 97359 | 0 | 0 |
T10 | 55014 | 54168 | 0 | 0 |
T24 | 710919 | 709842 | 0 | 0 |
T36 | 40191 | 40002 | 0 | 0 |
T37 | 4611 | 4353 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 53340480 | 53300889 | 0 | 0 |
gen_flops.OutputDelay_A | 53340480 | 53299089 | 0 | 666 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53299089 | 0 | 666 |
T1 | 113066 | 113004 | 0 | 3 |
T2 | 266423 | 266096 | 0 | 3 |
T3 | 338553 | 338278 | 0 | 3 |
T4 | 245207 | 244808 | 0 | 3 |
T8 | 73947 | 73883 | 0 | 3 |
T9 | 32503 | 32450 | 0 | 3 |
T10 | 18338 | 18044 | 0 | 3 |
T24 | 236973 | 236599 | 0 | 3 |
T36 | 13397 | 13331 | 0 | 3 |
T37 | 1537 | 1448 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 53340480 | 53300889 | 0 | 0 |
gen_flops.OutputDelay_A | 53340480 | 53299089 | 0 | 666 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53299089 | 0 | 666 |
T1 | 113066 | 113004 | 0 | 3 |
T2 | 266423 | 266096 | 0 | 3 |
T3 | 338553 | 338278 | 0 | 3 |
T4 | 245207 | 244808 | 0 | 3 |
T8 | 73947 | 73883 | 0 | 3 |
T9 | 32503 | 32450 | 0 | 3 |
T10 | 18338 | 18044 | 0 | 3 |
T24 | 236973 | 236599 | 0 | 3 |
T36 | 13397 | 13331 | 0 | 3 |
T37 | 1537 | 1448 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 53340480 | 53300889 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53340480 | 53300889 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 53340480 | 53300889 | 0 | 0 |
gen_flops.OutputDelay_A | 53340480 | 53299089 | 0 | 666 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53299089 | 0 | 666 |
T1 | 113066 | 113004 | 0 | 3 |
T2 | 266423 | 266096 | 0 | 3 |
T3 | 338553 | 338278 | 0 | 3 |
T4 | 245207 | 244808 | 0 | 3 |
T8 | 73947 | 73883 | 0 | 3 |
T9 | 32503 | 32450 | 0 | 3 |
T10 | 18338 | 18044 | 0 | 3 |
T24 | 236973 | 236599 | 0 | 3 |
T36 | 13397 | 13331 | 0 | 3 |
T37 | 1537 | 1448 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 53340480 | 53300889 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53340480 | 53300889 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 53340480 | 53300889 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53340480 | 53300889 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |