SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.91 | 96.97 | 59.57 | 90.53 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 222 | 222 | 0 | 0 |
OutputsKnown_A | 53340480 | 53300889 | 0 | 0 |
gen_no_flops.OutputDelay_A | 53340480 | 53300889 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222 | 222 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53340480 | 53300889 | 0 | 0 |
T1 | 113066 | 113007 | 0 | 0 |
T2 | 266423 | 266111 | 0 | 0 |
T3 | 338553 | 338290 | 0 | 0 |
T4 | 245207 | 244826 | 0 | 0 |
T8 | 73947 | 73886 | 0 | 0 |
T9 | 32503 | 32453 | 0 | 0 |
T10 | 18338 | 18056 | 0 | 0 |
T24 | 236973 | 236614 | 0 | 0 |
T36 | 13397 | 13334 | 0 | 0 |
T37 | 1537 | 1451 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |