SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
82.20 | 95.27 | 79.59 | 89.42 | 74.36 | 85.50 | 98.21 | 53.09 |
T307 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2403514847 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:31 PM PDT 24 | 9596309245 ps | ||
T90 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1675483285 | Jun 30 06:39:04 PM PDT 24 | Jun 30 06:39:08 PM PDT 24 | 217285579 ps | ||
T96 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.604976191 | Jun 30 06:38:24 PM PDT 24 | Jun 30 06:38:27 PM PDT 24 | 226173429 ps | ||
T91 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1312799134 | Jun 30 06:39:22 PM PDT 24 | Jun 30 06:39:28 PM PDT 24 | 572184453 ps | ||
T308 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4018551772 | Jun 30 06:39:18 PM PDT 24 | Jun 30 06:39:27 PM PDT 24 | 7694455491 ps | ||
T97 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.287682664 | Jun 30 06:38:44 PM PDT 24 | Jun 30 06:38:50 PM PDT 24 | 5555436233 ps | ||
T98 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2351064442 | Jun 30 06:39:09 PM PDT 24 | Jun 30 06:39:11 PM PDT 24 | 95802133 ps | ||
T107 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3318188220 | Jun 30 06:38:43 PM PDT 24 | Jun 30 06:39:43 PM PDT 24 | 22016872138 ps | ||
T92 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3046204253 | Jun 30 06:39:09 PM PDT 24 | Jun 30 06:39:12 PM PDT 24 | 95216222 ps | ||
T309 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1647846207 | Jun 30 06:39:21 PM PDT 24 | Jun 30 06:39:55 PM PDT 24 | 11554275763 ps | ||
T93 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2263335999 | Jun 30 06:39:16 PM PDT 24 | Jun 30 06:39:19 PM PDT 24 | 86307172 ps | ||
T99 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.604957985 | Jun 30 06:38:45 PM PDT 24 | Jun 30 06:38:47 PM PDT 24 | 105491920 ps | ||
T100 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2351677948 | Jun 30 06:38:29 PM PDT 24 | Jun 30 06:40:03 PM PDT 24 | 51263137190 ps | ||
T101 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2875414281 | Jun 30 06:38:28 PM PDT 24 | Jun 30 06:38:31 PM PDT 24 | 84860462 ps | ||
T310 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.278838404 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:41:19 PM PDT 24 | 53203394303 ps | ||
T103 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.595011453 | Jun 30 06:38:39 PM PDT 24 | Jun 30 06:38:43 PM PDT 24 | 776144292 ps | ||
T104 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2336923931 | Jun 30 06:38:58 PM PDT 24 | Jun 30 06:39:20 PM PDT 24 | 5996830576 ps | ||
T102 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4188789725 | Jun 30 06:38:22 PM PDT 24 | Jun 30 06:39:19 PM PDT 24 | 5883137867 ps | ||
T134 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2864548232 | Jun 30 06:39:10 PM PDT 24 | Jun 30 06:39:30 PM PDT 24 | 5080921928 ps | ||
T311 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1155170966 | Jun 30 06:39:03 PM PDT 24 | Jun 30 06:39:04 PM PDT 24 | 176455406 ps | ||
T312 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1527965301 | Jun 30 06:38:10 PM PDT 24 | Jun 30 06:38:23 PM PDT 24 | 4379372190 ps | ||
T313 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.189823230 | Jun 30 06:38:51 PM PDT 24 | Jun 30 06:38:58 PM PDT 24 | 4270313146 ps | ||
T314 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1535342042 | Jun 30 06:39:04 PM PDT 24 | Jun 30 06:39:10 PM PDT 24 | 4619289359 ps | ||
T110 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3304014044 | Jun 30 06:39:24 PM PDT 24 | Jun 30 06:39:30 PM PDT 24 | 157698824 ps | ||
T135 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3725107357 | Jun 30 06:38:58 PM PDT 24 | Jun 30 06:39:02 PM PDT 24 | 1177443827 ps | ||
T315 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1269732755 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:11 PM PDT 24 | 1040740630 ps | ||
T316 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2975095906 | Jun 30 06:38:51 PM PDT 24 | Jun 30 06:39:09 PM PDT 24 | 6953825278 ps | ||
T64 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2203675164 | Jun 30 06:38:52 PM PDT 24 | Jun 30 06:39:19 PM PDT 24 | 53197895507 ps | ||
T172 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3498539653 | Jun 30 06:38:46 PM PDT 24 | Jun 30 06:39:06 PM PDT 24 | 5689497366 ps | ||
T317 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2373158523 | Jun 30 06:38:47 PM PDT 24 | Jun 30 06:39:08 PM PDT 24 | 7997902598 ps | ||
T170 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3307455579 | Jun 30 06:38:11 PM PDT 24 | Jun 30 06:38:28 PM PDT 24 | 2064391615 ps | ||
T318 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.472998793 | Jun 30 06:38:39 PM PDT 24 | Jun 30 06:39:23 PM PDT 24 | 16412598638 ps | ||
T319 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.734643383 | Jun 30 06:38:30 PM PDT 24 | Jun 30 06:39:25 PM PDT 24 | 23511669143 ps | ||
T320 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2151455773 | Jun 30 06:38:29 PM PDT 24 | Jun 30 06:38:48 PM PDT 24 | 12040332303 ps | ||
T321 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1362038436 | Jun 30 06:38:43 PM PDT 24 | Jun 30 06:38:45 PM PDT 24 | 96590012 ps | ||
T136 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4115795943 | Jun 30 06:39:09 PM PDT 24 | Jun 30 06:39:12 PM PDT 24 | 155144611 ps | ||
T322 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2388504440 | Jun 30 06:39:16 PM PDT 24 | Jun 30 06:39:17 PM PDT 24 | 114200895 ps | ||
T124 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3247919846 | Jun 30 06:39:11 PM PDT 24 | Jun 30 06:39:16 PM PDT 24 | 421240354 ps | ||
T323 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.764225944 | Jun 30 06:39:27 PM PDT 24 | Jun 30 06:39:30 PM PDT 24 | 288024596 ps | ||
T324 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.357207319 | Jun 30 06:39:09 PM PDT 24 | Jun 30 06:39:46 PM PDT 24 | 13455675274 ps | ||
T325 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2855700792 | Jun 30 06:38:33 PM PDT 24 | Jun 30 06:38:34 PM PDT 24 | 144667838 ps | ||
T111 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4116632263 | Jun 30 06:38:16 PM PDT 24 | Jun 30 06:38:25 PM PDT 24 | 542014299 ps | ||
T173 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.869941843 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:24 PM PDT 24 | 748417870 ps | ||
T326 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2493148369 | Jun 30 06:38:17 PM PDT 24 | Jun 30 06:38:19 PM PDT 24 | 293890210 ps | ||
T112 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2129907368 | Jun 30 06:39:05 PM PDT 24 | Jun 30 06:39:08 PM PDT 24 | 123888610 ps | ||
T327 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1622465892 | Jun 30 06:39:07 PM PDT 24 | Jun 30 06:39:09 PM PDT 24 | 1059987674 ps | ||
T113 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.165390552 | Jun 30 06:39:10 PM PDT 24 | Jun 30 06:39:13 PM PDT 24 | 207726132 ps | ||
T328 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2666578824 | Jun 30 06:39:03 PM PDT 24 | Jun 30 06:39:12 PM PDT 24 | 1305015438 ps | ||
T329 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.669060001 | Jun 30 06:38:57 PM PDT 24 | Jun 30 06:39:01 PM PDT 24 | 1586580493 ps | ||
T330 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2464087143 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:18 PM PDT 24 | 135038474 ps | ||
T331 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3388615783 | Jun 30 06:39:17 PM PDT 24 | Jun 30 06:39:38 PM PDT 24 | 4466926713 ps | ||
T167 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1229226392 | Jun 30 06:38:52 PM PDT 24 | Jun 30 06:38:58 PM PDT 24 | 184971737 ps | ||
T332 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4250485654 | Jun 30 06:39:24 PM PDT 24 | Jun 30 06:39:26 PM PDT 24 | 545481779 ps | ||
T333 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2768118171 | Jun 30 06:39:03 PM PDT 24 | Jun 30 06:39:05 PM PDT 24 | 2150743427 ps | ||
T129 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2658644773 | Jun 30 06:38:57 PM PDT 24 | Jun 30 06:39:00 PM PDT 24 | 277044573 ps | ||
T334 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1816260041 | Jun 30 06:38:27 PM PDT 24 | Jun 30 06:38:29 PM PDT 24 | 1394223172 ps | ||
T174 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3322636467 | Jun 30 06:38:57 PM PDT 24 | Jun 30 06:39:16 PM PDT 24 | 3386404167 ps | ||
T335 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2388355019 | Jun 30 06:38:21 PM PDT 24 | Jun 30 06:38:23 PM PDT 24 | 39431963 ps | ||
T336 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3272384120 | Jun 30 06:38:28 PM PDT 24 | Jun 30 06:38:29 PM PDT 24 | 314775446 ps | ||
T337 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.383585346 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:11 PM PDT 24 | 212673979 ps | ||
T125 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2159949340 | Jun 30 06:38:51 PM PDT 24 | Jun 30 06:38:56 PM PDT 24 | 1056650173 ps | ||
T338 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1221223228 | Jun 30 06:38:10 PM PDT 24 | Jun 30 06:38:13 PM PDT 24 | 720596918 ps | ||
T339 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1367339959 | Jun 30 06:39:24 PM PDT 24 | Jun 30 06:39:25 PM PDT 24 | 306950611 ps | ||
T340 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1494252196 | Jun 30 06:39:11 PM PDT 24 | Jun 30 06:39:16 PM PDT 24 | 725540264 ps | ||
T341 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2413706620 | Jun 30 06:39:23 PM PDT 24 | Jun 30 06:39:25 PM PDT 24 | 762729654 ps | ||
T342 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3757928398 | Jun 30 06:38:24 PM PDT 24 | Jun 30 06:38:40 PM PDT 24 | 11880280030 ps | ||
T181 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.444399809 | Jun 30 06:38:34 PM PDT 24 | Jun 30 06:39:16 PM PDT 24 | 44317199133 ps | ||
T114 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1348237737 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:18 PM PDT 24 | 72137077 ps | ||
T343 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3165974304 | Jun 30 06:38:11 PM PDT 24 | Jun 30 06:38:47 PM PDT 24 | 45203043598 ps | ||
T344 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2462075465 | Jun 30 06:39:22 PM PDT 24 | Jun 30 06:39:25 PM PDT 24 | 1316193447 ps | ||
T345 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2533744522 | Jun 30 06:38:21 PM PDT 24 | Jun 30 06:38:27 PM PDT 24 | 317695391 ps | ||
T118 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2032190217 | Jun 30 06:39:03 PM PDT 24 | Jun 30 06:39:06 PM PDT 24 | 153447572 ps | ||
T346 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4151549111 | Jun 30 06:38:10 PM PDT 24 | Jun 30 06:38:11 PM PDT 24 | 2076691991 ps | ||
T108 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2039750011 | Jun 30 06:38:09 PM PDT 24 | Jun 30 06:38:12 PM PDT 24 | 2832157634 ps | ||
T119 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.388843292 | Jun 30 06:38:22 PM PDT 24 | Jun 30 06:38:51 PM PDT 24 | 2338568088 ps | ||
T347 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.625776294 | Jun 30 06:38:19 PM PDT 24 | Jun 30 06:38:25 PM PDT 24 | 2908948195 ps | ||
T115 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1029825616 | Jun 30 06:39:03 PM PDT 24 | Jun 30 06:39:14 PM PDT 24 | 1940870407 ps | ||
T348 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1030736978 | Jun 30 06:38:17 PM PDT 24 | Jun 30 06:38:22 PM PDT 24 | 138888007 ps | ||
T120 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2855220368 | Jun 30 06:39:28 PM PDT 24 | Jun 30 06:39:30 PM PDT 24 | 84826337 ps | ||
T349 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.756553242 | Jun 30 06:38:34 PM PDT 24 | Jun 30 06:38:35 PM PDT 24 | 70823673 ps | ||
T126 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1240581446 | Jun 30 06:38:34 PM PDT 24 | Jun 30 06:38:42 PM PDT 24 | 1485635534 ps | ||
T350 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3869276037 | Jun 30 06:39:05 PM PDT 24 | Jun 30 06:39:10 PM PDT 24 | 2941057065 ps | ||
T351 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1074261550 | Jun 30 06:38:23 PM PDT 24 | Jun 30 06:38:26 PM PDT 24 | 1713067940 ps | ||
T352 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4229626793 | Jun 30 06:38:57 PM PDT 24 | Jun 30 06:39:02 PM PDT 24 | 2367012504 ps | ||
T353 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1561073280 | Jun 30 06:38:58 PM PDT 24 | Jun 30 06:39:06 PM PDT 24 | 3105345137 ps | ||
T354 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2060391062 | Jun 30 06:38:44 PM PDT 24 | Jun 30 06:38:46 PM PDT 24 | 184559957 ps | ||
T355 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3170241768 | Jun 30 06:38:21 PM PDT 24 | Jun 30 06:38:22 PM PDT 24 | 166508028 ps | ||
T356 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1142561906 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:35 PM PDT 24 | 10174965873 ps | ||
T357 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3208725290 | Jun 30 06:38:15 PM PDT 24 | Jun 30 06:38:16 PM PDT 24 | 645637946 ps | ||
T358 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1416401309 | Jun 30 06:39:26 PM PDT 24 | Jun 30 06:39:31 PM PDT 24 | 5055945993 ps | ||
T359 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.269982266 | Jun 30 06:38:58 PM PDT 24 | Jun 30 06:39:04 PM PDT 24 | 181624419 ps | ||
T360 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1439438703 | Jun 30 06:38:33 PM PDT 24 | Jun 30 06:38:35 PM PDT 24 | 153581446 ps | ||
T361 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.26433432 | Jun 30 06:38:16 PM PDT 24 | Jun 30 06:38:17 PM PDT 24 | 85336375 ps | ||
T168 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3487993 | Jun 30 06:39:20 PM PDT 24 | Jun 30 06:39:37 PM PDT 24 | 882824051 ps | ||
T362 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3591263355 | Jun 30 06:39:26 PM PDT 24 | Jun 30 06:39:30 PM PDT 24 | 1550956255 ps | ||
T363 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.660773275 | Jun 30 06:38:27 PM PDT 24 | Jun 30 06:38:31 PM PDT 24 | 347657388 ps | ||
T127 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3506655804 | Jun 30 06:38:56 PM PDT 24 | Jun 30 06:39:04 PM PDT 24 | 1432150058 ps | ||
T364 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1543573985 | Jun 30 06:39:25 PM PDT 24 | Jun 30 06:39:28 PM PDT 24 | 485761774 ps | ||
T175 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3094569457 | Jun 30 06:39:22 PM PDT 24 | Jun 30 06:39:32 PM PDT 24 | 507433853 ps | ||
T365 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2909974537 | Jun 30 06:39:06 PM PDT 24 | Jun 30 06:39:14 PM PDT 24 | 2331584725 ps | ||
T366 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1207088479 | Jun 30 06:38:19 PM PDT 24 | Jun 30 06:38:40 PM PDT 24 | 29768218566 ps | ||
T367 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.551469852 | Jun 30 06:38:57 PM PDT 24 | Jun 30 06:39:00 PM PDT 24 | 489707035 ps | ||
T368 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1263115483 | Jun 30 06:39:03 PM PDT 24 | Jun 30 06:39:07 PM PDT 24 | 152482124 ps | ||
T369 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.310211155 | Jun 30 06:38:09 PM PDT 24 | Jun 30 06:38:16 PM PDT 24 | 2019450428 ps | ||
T370 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3444582310 | Jun 30 06:39:22 PM PDT 24 | Jun 30 06:39:24 PM PDT 24 | 123541686 ps | ||
T371 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.988903850 | Jun 30 06:39:17 PM PDT 24 | Jun 30 06:39:18 PM PDT 24 | 178852350 ps | ||
T372 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.8464557 | Jun 30 06:38:43 PM PDT 24 | Jun 30 06:38:49 PM PDT 24 | 6402586090 ps | ||
T373 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.828783518 | Jun 30 06:39:04 PM PDT 24 | Jun 30 06:39:09 PM PDT 24 | 586851412 ps | ||
T374 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3036820965 | Jun 30 06:38:17 PM PDT 24 | Jun 30 06:38:47 PM PDT 24 | 1760670824 ps | ||
T121 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2926956475 | Jun 30 06:38:10 PM PDT 24 | Jun 30 06:38:38 PM PDT 24 | 596147333 ps | ||
T375 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3751957564 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:40:05 PM PDT 24 | 20265489758 ps | ||
T376 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.552852021 | Jun 30 06:38:44 PM PDT 24 | Jun 30 06:38:45 PM PDT 24 | 124875279 ps | ||
T377 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3306803194 | Jun 30 06:38:39 PM PDT 24 | Jun 30 06:38:42 PM PDT 24 | 1700063723 ps | ||
T122 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3336488177 | Jun 30 06:38:59 PM PDT 24 | Jun 30 06:39:01 PM PDT 24 | 238427103 ps | ||
T378 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3600206115 | Jun 30 06:38:35 PM PDT 24 | Jun 30 06:38:53 PM PDT 24 | 6624395013 ps | ||
T123 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.680191177 | Jun 30 06:39:03 PM PDT 24 | Jun 30 06:39:06 PM PDT 24 | 366465612 ps | ||
T379 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2273367968 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:14 PM PDT 24 | 399318289 ps | ||
T380 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.87460604 | Jun 30 06:38:40 PM PDT 24 | Jun 30 06:38:41 PM PDT 24 | 666168781 ps | ||
T179 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2493251217 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:18 PM PDT 24 | 1619389204 ps | ||
T176 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1660149303 | Jun 30 06:38:50 PM PDT 24 | Jun 30 06:39:09 PM PDT 24 | 5606502535 ps | ||
T381 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1094794139 | Jun 30 06:38:45 PM PDT 24 | Jun 30 06:38:46 PM PDT 24 | 52400263 ps | ||
T382 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2218226238 | Jun 30 06:38:51 PM PDT 24 | Jun 30 06:38:56 PM PDT 24 | 2074763923 ps | ||
T383 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1137284410 | Jun 30 06:38:18 PM PDT 24 | Jun 30 06:38:20 PM PDT 24 | 855316732 ps | ||
T384 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.4023693453 | Jun 30 06:39:25 PM PDT 24 | Jun 30 06:39:28 PM PDT 24 | 193342227 ps | ||
T128 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2018517914 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:13 PM PDT 24 | 456896700 ps | ||
T385 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2486914422 | Jun 30 06:38:52 PM PDT 24 | Jun 30 06:38:54 PM PDT 24 | 1554782483 ps | ||
T386 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.90979300 | Jun 30 06:38:23 PM PDT 24 | Jun 30 06:38:26 PM PDT 24 | 614136263 ps | ||
T180 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3952898551 | Jun 30 06:38:59 PM PDT 24 | Jun 30 06:39:10 PM PDT 24 | 1877912535 ps | ||
T387 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2589695190 | Jun 30 06:38:17 PM PDT 24 | Jun 30 06:38:50 PM PDT 24 | 9880973427 ps | ||
T177 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.70152147 | Jun 30 06:39:26 PM PDT 24 | Jun 30 06:39:37 PM PDT 24 | 2018938671 ps | ||
T388 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.985183985 | Jun 30 06:38:40 PM PDT 24 | Jun 30 06:39:13 PM PDT 24 | 3278497740 ps | ||
T389 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2753628501 | Jun 30 06:39:21 PM PDT 24 | Jun 30 06:39:32 PM PDT 24 | 11482692561 ps | ||
T390 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1962566476 | Jun 30 06:38:46 PM PDT 24 | Jun 30 06:38:55 PM PDT 24 | 6313180434 ps | ||
T391 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1537720578 | Jun 30 06:38:39 PM PDT 24 | Jun 30 06:38:54 PM PDT 24 | 4805682264 ps | ||
T392 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3147421407 | Jun 30 06:38:10 PM PDT 24 | Jun 30 06:38:11 PM PDT 24 | 210532750 ps | ||
T393 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3224323101 | Jun 30 06:39:04 PM PDT 24 | Jun 30 06:39:22 PM PDT 24 | 6081090870 ps | ||
T109 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.636153246 | Jun 30 06:38:19 PM PDT 24 | Jun 30 06:38:25 PM PDT 24 | 1848040436 ps | ||
T394 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2369460955 | Jun 30 06:38:10 PM PDT 24 | Jun 30 06:38:13 PM PDT 24 | 1559975630 ps | ||
T395 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.396720164 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:26 PM PDT 24 | 3122530027 ps | ||
T396 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1751315408 | Jun 30 06:38:51 PM PDT 24 | Jun 30 06:39:07 PM PDT 24 | 18711388854 ps | ||
T397 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3869244503 | Jun 30 06:38:28 PM PDT 24 | Jun 30 06:38:30 PM PDT 24 | 225099882 ps | ||
T398 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2691295665 | Jun 30 06:38:33 PM PDT 24 | Jun 30 06:39:02 PM PDT 24 | 1745066144 ps | ||
T399 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3522962667 | Jun 30 06:39:01 PM PDT 24 | Jun 30 06:39:02 PM PDT 24 | 177618094 ps | ||
T400 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2698958738 | Jun 30 06:38:57 PM PDT 24 | Jun 30 06:39:25 PM PDT 24 | 14606853270 ps | ||
T401 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3307316911 | Jun 30 06:38:27 PM PDT 24 | Jun 30 06:38:31 PM PDT 24 | 266430728 ps | ||
T402 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3787671715 | Jun 30 06:38:17 PM PDT 24 | Jun 30 06:38:20 PM PDT 24 | 381929305 ps | ||
T403 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.513194215 | Jun 30 06:38:20 PM PDT 24 | Jun 30 06:38:30 PM PDT 24 | 1716089535 ps | ||
T404 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2605422845 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:21 PM PDT 24 | 138500077 ps | ||
T405 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4022385805 | Jun 30 06:38:34 PM PDT 24 | Jun 30 06:38:38 PM PDT 24 | 170786669 ps | ||
T406 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3972657545 | Jun 30 06:38:58 PM PDT 24 | Jun 30 06:39:24 PM PDT 24 | 26266948290 ps | ||
T407 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2002168462 | Jun 30 06:38:38 PM PDT 24 | Jun 30 06:38:44 PM PDT 24 | 5155246037 ps | ||
T116 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1341717142 | Jun 30 06:39:01 PM PDT 24 | Jun 30 06:39:08 PM PDT 24 | 1271028365 ps | ||
T408 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.885265518 | Jun 30 06:39:06 PM PDT 24 | Jun 30 06:39:13 PM PDT 24 | 288318633 ps | ||
T409 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.929965423 | Jun 30 06:39:26 PM PDT 24 | Jun 30 06:39:28 PM PDT 24 | 253310419 ps | ||
T410 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2028570246 | Jun 30 06:38:47 PM PDT 24 | Jun 30 06:39:58 PM PDT 24 | 10202221931 ps | ||
T411 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2391809130 | Jun 30 06:39:28 PM PDT 24 | Jun 30 06:39:32 PM PDT 24 | 89815622 ps | ||
T412 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1813314388 | Jun 30 06:38:58 PM PDT 24 | Jun 30 06:39:57 PM PDT 24 | 61612600726 ps | ||
T413 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3302642548 | Jun 30 06:38:29 PM PDT 24 | Jun 30 06:38:32 PM PDT 24 | 399576730 ps | ||
T414 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1912798034 | Jun 30 06:39:22 PM PDT 24 | Jun 30 06:39:45 PM PDT 24 | 34233606859 ps | ||
T415 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1148338277 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:23 PM PDT 24 | 1539890959 ps | ||
T416 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.10016987 | Jun 30 06:38:52 PM PDT 24 | Jun 30 06:38:54 PM PDT 24 | 249255514 ps | ||
T417 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1251568501 | Jun 30 06:38:09 PM PDT 24 | Jun 30 06:41:58 PM PDT 24 | 96480872456 ps | ||
T418 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.934138200 | Jun 30 06:38:19 PM PDT 24 | Jun 30 06:39:29 PM PDT 24 | 72197861139 ps | ||
T419 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1371261562 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:11 PM PDT 24 | 300836921 ps | ||
T420 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1363965709 | Jun 30 06:38:15 PM PDT 24 | Jun 30 06:38:17 PM PDT 24 | 330044597 ps | ||
T421 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3977936978 | Jun 30 06:38:22 PM PDT 24 | Jun 30 06:38:23 PM PDT 24 | 45362027 ps | ||
T422 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1826814203 | Jun 30 06:38:32 PM PDT 24 | Jun 30 06:39:40 PM PDT 24 | 23258896826 ps | ||
T423 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1710508898 | Jun 30 06:38:09 PM PDT 24 | Jun 30 06:38:10 PM PDT 24 | 58384435 ps | ||
T424 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2854276317 | Jun 30 06:39:08 PM PDT 24 | Jun 30 06:39:13 PM PDT 24 | 119181586 ps | ||
T171 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.420923835 | Jun 30 06:38:28 PM PDT 24 | Jun 30 06:38:44 PM PDT 24 | 4643199077 ps | ||
T182 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1797645450 | Jun 30 06:38:46 PM PDT 24 | Jun 30 06:39:12 PM PDT 24 | 29208523725 ps | ||
T425 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.247272153 | Jun 30 06:38:41 PM PDT 24 | Jun 30 06:39:24 PM PDT 24 | 46446516551 ps | ||
T426 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.712463627 | Jun 30 06:38:51 PM PDT 24 | Jun 30 06:38:53 PM PDT 24 | 228971375 ps | ||
T427 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.514629013 | Jun 30 06:39:12 PM PDT 24 | Jun 30 06:39:22 PM PDT 24 | 4189145567 ps | ||
T428 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1595226258 | Jun 30 06:39:22 PM PDT 24 | Jun 30 06:39:25 PM PDT 24 | 834286849 ps | ||
T429 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.405698251 | Jun 30 06:39:23 PM PDT 24 | Jun 30 06:39:28 PM PDT 24 | 2637532769 ps | ||
T430 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3816346417 | Jun 30 06:38:33 PM PDT 24 | Jun 30 06:38:36 PM PDT 24 | 747363304 ps | ||
T169 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2914193481 | Jun 30 06:38:37 PM PDT 24 | Jun 30 06:39:00 PM PDT 24 | 3886735569 ps | ||
T431 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3259589596 | Jun 30 06:38:29 PM PDT 24 | Jun 30 06:38:31 PM PDT 24 | 138464283 ps | ||
T432 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1289655897 | Jun 30 06:38:08 PM PDT 24 | Jun 30 06:40:19 PM PDT 24 | 45900023118 ps | ||
T433 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3251774840 | Jun 30 06:39:15 PM PDT 24 | Jun 30 06:39:20 PM PDT 24 | 460687921 ps | ||
T434 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2831362781 | Jun 30 06:38:45 PM PDT 24 | Jun 30 06:38:56 PM PDT 24 | 11757466039 ps | ||
T178 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2957687187 | Jun 30 06:38:44 PM PDT 24 | Jun 30 06:38:56 PM PDT 24 | 2414861559 ps | ||
T435 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3112782117 | Jun 30 06:38:45 PM PDT 24 | Jun 30 06:38:48 PM PDT 24 | 241442969 ps | ||
T436 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.24421113 | Jun 30 06:38:33 PM PDT 24 | Jun 30 06:39:03 PM PDT 24 | 17773228283 ps | ||
T437 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.81867808 | Jun 30 06:39:04 PM PDT 24 | Jun 30 06:39:09 PM PDT 24 | 116583392 ps | ||
T117 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3860398578 | Jun 30 06:38:46 PM PDT 24 | Jun 30 06:38:49 PM PDT 24 | 658733071 ps | ||
T438 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1943060707 | Jun 30 06:39:09 PM PDT 24 | Jun 30 06:39:22 PM PDT 24 | 5107239209 ps | ||
T439 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2286523868 | Jun 30 06:38:22 PM PDT 24 | Jun 30 06:38:27 PM PDT 24 | 222632486 ps | ||
T440 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1825519434 | Jun 30 06:39:07 PM PDT 24 | Jun 30 06:39:09 PM PDT 24 | 1520552209 ps | ||
T441 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.166844428 | Jun 30 06:38:22 PM PDT 24 | Jun 30 06:38:34 PM PDT 24 | 5333969446 ps | ||
T442 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.758522514 | Jun 30 06:38:27 PM PDT 24 | Jun 30 06:38:34 PM PDT 24 | 622440646 ps |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.508177890 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 9517560457 ps |
CPU time | 7.07 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:13 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-559ef390-3dcc-4ccb-883b-0dfb3c5ecd13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508177890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.508177890 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1645504022 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 4216809282 ps |
CPU time | 11.59 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-f949dd3e-5203-488c-9b11-1f328552d815 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645504022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1645504022 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.238528369 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 561750177 ps |
CPU time | 5.66 seconds |
Started | Jun 30 06:39:00 PM PDT 24 |
Finished | Jun 30 06:39:07 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-0d836783-8c15-4f80-9e03-f198c7f685f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238528369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.238528369 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.4045251016 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 6158683149 ps |
CPU time | 15.54 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:32 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-8444b896-991e-45c3-b0e0-5358aa924484 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045251016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.4045251016 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2203675164 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 53197895507 ps |
CPU time | 25.91 seconds |
Started | Jun 30 06:38:52 PM PDT 24 |
Finished | Jun 30 06:39:19 PM PDT 24 |
Peak memory | 229580 kb |
Host | smart-657eda5e-db18-4294-b29b-7abc2f6ead75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203675164 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2203675164 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.125164318 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 1779536061 ps |
CPU time | 11.03 seconds |
Started | Jun 30 06:39:06 PM PDT 24 |
Finished | Jun 30 06:39:18 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-c3f4fc57-2d27-4cf2-a325-91cf893024ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125164318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.125164318 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.1683313089 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 8663486269 ps |
CPU time | 16.06 seconds |
Started | Jun 30 06:40:17 PM PDT 24 |
Finished | Jun 30 06:40:34 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-88127001-3be0-4f94-8bf0-135a11824781 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683313089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1683313089 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.4083734609 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 96475665 ps |
CPU time | 0.93 seconds |
Started | Jun 30 06:39:52 PM PDT 24 |
Finished | Jun 30 06:39:54 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-5b7a15d6-baae-472c-80be-55bebc1c0f68 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083734609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.4083734609 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.983462254 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 20081580723 ps |
CPU time | 35.08 seconds |
Started | Jun 30 06:40:01 PM PDT 24 |
Finished | Jun 30 06:40:37 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-f3025d7a-6310-4e25-aa5c-527e8df874e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983462254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.983462254 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.2415427979 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 103270377 ps |
CPU time | 0.95 seconds |
Started | Jun 30 06:39:40 PM PDT 24 |
Finished | Jun 30 06:39:42 PM PDT 24 |
Peak memory | 215584 kb |
Host | smart-49cc9fdf-6b05-4848-8fc1-4ed78c48034f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415427979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2415427979 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.1900378660 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 642278738 ps |
CPU time | 2.61 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:38 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-1cdab45e-73d7-42c2-95fd-d5db5fb422ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900378660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1900378660 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.702942156 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 8314773337 ps |
CPU time | 24.11 seconds |
Started | Jun 30 06:40:20 PM PDT 24 |
Finished | Jun 30 06:40:45 PM PDT 24 |
Peak memory | 212820 kb |
Host | smart-da00c097-a84b-45ff-8af7-2aa2b1cbd1dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702942156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.702942156 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2557283929 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 3266461920 ps |
CPU time | 5.85 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:06 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-8c34c3ef-e364-43ce-9170-01716d34dfed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557283929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2557283929 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2351677948 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 51263137190 ps |
CPU time | 93.82 seconds |
Started | Jun 30 06:38:29 PM PDT 24 |
Finished | Jun 30 06:40:03 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-a59f0c88-47e9-4d39-b644-b5ef0919035a |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351677948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.2351677948 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.1075925439 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 120023987 ps |
CPU time | 1.06 seconds |
Started | Jun 30 06:39:36 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 213192 kb |
Host | smart-e4800811-ee90-4413-9d99-c3e5a48edd30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075925439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1075925439 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.1719506702 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 2078421724 ps |
CPU time | 6.61 seconds |
Started | Jun 30 06:39:35 PM PDT 24 |
Finished | Jun 30 06:39:42 PM PDT 24 |
Peak memory | 237076 kb |
Host | smart-bee445a3-8ac9-41c5-92dc-5381f92927a8 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719506702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1719506702 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.2768777125 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 1678607115 ps |
CPU time | 3.08 seconds |
Started | Jun 30 06:39:39 PM PDT 24 |
Finished | Jun 30 06:39:42 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-9f5dbfd7-18a8-4be3-b9b2-59a454d0a664 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768777125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2768777125 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1795563939 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 9671449632 ps |
CPU time | 12.92 seconds |
Started | Jun 30 06:39:48 PM PDT 24 |
Finished | Jun 30 06:40:02 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-b8ddd0b6-b6aa-4c80-92b7-d6b3b04487ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795563939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1795563939 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.3951917213 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 6383721808 ps |
CPU time | 16.38 seconds |
Started | Jun 30 06:40:20 PM PDT 24 |
Finished | Jun 30 06:40:37 PM PDT 24 |
Peak memory | 213064 kb |
Host | smart-a83d4be7-90b6-429a-ac13-c73c87eb8201 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951917213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3951917213 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.2032262087 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 119005778 ps |
CPU time | 0.75 seconds |
Started | Jun 30 06:39:37 PM PDT 24 |
Finished | Jun 30 06:39:38 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-87cfe3d5-c6c3-43ee-8be0-a5cdaf9e5b5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032262087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2032262087 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.420923835 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 4643199077 ps |
CPU time | 15.59 seconds |
Started | Jun 30 06:38:28 PM PDT 24 |
Finished | Jun 30 06:38:44 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-5aafc852-b8d0-42ef-b1c0-958b4c8899ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420923835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.420923835 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.4156115799 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 477282836 ps |
CPU time | 0.87 seconds |
Started | Jun 30 06:39:39 PM PDT 24 |
Finished | Jun 30 06:39:40 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-f835540e-fb7c-4c2d-8ef4-d6ce3d7b1098 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156115799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.4156115799 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2551520776 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 183414112 ps |
CPU time | 0.95 seconds |
Started | Jun 30 06:39:32 PM PDT 24 |
Finished | Jun 30 06:39:33 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-785d483a-ed75-491a-a292-6a95794693d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551520776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2551520776 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2238250420 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 29102110386 ps |
CPU time | 44.68 seconds |
Started | Jun 30 06:38:30 PM PDT 24 |
Finished | Jun 30 06:39:15 PM PDT 24 |
Peak memory | 221512 kb |
Host | smart-34ab9d7e-43cc-4281-8c5c-1e5c9ed54a1a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238250420 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2238250420 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3487993 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 882824051 ps |
CPU time | 17.12 seconds |
Started | Jun 30 06:39:20 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-dfd5206b-f790-4942-b483-56dafc1e8d64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3487993 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.1107452006 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 4861814170 ps |
CPU time | 4.2 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-7ea859c0-aa84-44dd-9fbb-32a2b807a650 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107452006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1107452006 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1261471915 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 26932939933 ps |
CPU time | 28.48 seconds |
Started | Jun 30 06:39:46 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-d3f34e95-0050-4d8c-bd91-c7380f26e2a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261471915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1261471915 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.869941843 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 748417870 ps |
CPU time | 8.75 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:24 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-4270ac8c-aec0-4967-8eca-1df4cfe2769a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869941843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.869941843 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.3377133469 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 10849749356 ps |
CPU time | 10.66 seconds |
Started | Jun 30 06:39:54 PM PDT 24 |
Finished | Jun 30 06:40:05 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-fe09b1f2-cdd4-495a-ab73-a64f74284c49 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377133469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3377133469 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1153418391 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 5241849763 ps |
CPU time | 14.65 seconds |
Started | Jun 30 06:38:17 PM PDT 24 |
Finished | Jun 30 06:38:32 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-04ca4b6c-e2a2-4f17-b5e4-88f4b0103251 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153418391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.1153418391 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2039750011 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 2832157634 ps |
CPU time | 2.5 seconds |
Started | Jun 30 06:38:09 PM PDT 24 |
Finished | Jun 30 06:38:12 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-2524b8c7-f51c-4962-bff7-247e5f8ca36e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039750011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2039750011 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4116632263 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 542014299 ps |
CPU time | 8.75 seconds |
Started | Jun 30 06:38:16 PM PDT 24 |
Finished | Jun 30 06:38:25 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-bbf4852d-5fd6-4d30-b574-7dac400cd0ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116632263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.4116632263 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1348237737 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 72137077 ps |
CPU time | 2.28 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:18 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-c138e0a7-507c-457b-beb2-5eefb83aabe2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348237737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1348237737 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2073410015 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1077843863 ps |
CPU time | 3.18 seconds |
Started | Jun 30 06:39:30 PM PDT 24 |
Finished | Jun 30 06:39:34 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-f78bc950-4e17-4048-82c7-3936b0aaa430 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073410015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2073410015 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1148338277 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 1539890959 ps |
CPU time | 7.17 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:23 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-c22ae795-a183-492c-8a4d-a45776a3a94a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148338277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1148338277 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1660149303 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 5606502535 ps |
CPU time | 17.99 seconds |
Started | Jun 30 06:38:50 PM PDT 24 |
Finished | Jun 30 06:39:09 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-185ffd88-30d9-4971-83fd-6e1865698db4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660149303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1660149303 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.898056758 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 106125535 ps |
CPU time | 1.01 seconds |
Started | Jun 30 06:39:33 PM PDT 24 |
Finished | Jun 30 06:39:35 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-45ad83b1-c9d3-47da-83b1-aae94eac5976 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=898056758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.898056758 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.1688607407 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 4146188365 ps |
CPU time | 11.54 seconds |
Started | Jun 30 06:40:08 PM PDT 24 |
Finished | Jun 30 06:40:20 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-1b694488-fdaf-4e42-ad5e-00f9645f1839 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1688607407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1688607407 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1113027576 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 12433460734 ps |
CPU time | 24.11 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:40:13 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-9e99044d-fbb1-4fa1-a2f0-2c4742c208a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113027576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1113027576 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2926956475 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 596147333 ps |
CPU time | 27.44 seconds |
Started | Jun 30 06:38:10 PM PDT 24 |
Finished | Jun 30 06:38:38 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-eae44083-6ec4-439f-a20c-0d93faf4a87d |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926956475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.2926956475 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2589695190 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 9880973427 ps |
CPU time | 32.87 seconds |
Started | Jun 30 06:38:17 PM PDT 24 |
Finished | Jun 30 06:38:50 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-fa653fb4-e308-421f-8144-f7d469569cc8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589695190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2589695190 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1363965709 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 330044597 ps |
CPU time | 1.63 seconds |
Started | Jun 30 06:38:15 PM PDT 24 |
Finished | Jun 30 06:38:17 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-240fdd0c-1710-4d0a-9c33-ef8530e3dfcd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363965709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1363965709 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1030736978 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 138888007 ps |
CPU time | 3.96 seconds |
Started | Jun 30 06:38:17 PM PDT 24 |
Finished | Jun 30 06:38:22 PM PDT 24 |
Peak memory | 219628 kb |
Host | smart-67456735-00a3-4c2c-9988-831d7f82f98b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030736978 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1030736978 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3787671715 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 381929305 ps |
CPU time | 2.51 seconds |
Started | Jun 30 06:38:17 PM PDT 24 |
Finished | Jun 30 06:38:20 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-5a21187d-6164-4afa-bffa-dcc24e92db81 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787671715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3787671715 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1251568501 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 96480872456 ps |
CPU time | 228.15 seconds |
Started | Jun 30 06:38:09 PM PDT 24 |
Finished | Jun 30 06:41:58 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-3f27891c-7f6c-45fe-887c-a5cb5bd95c91 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251568501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1251568501 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1527965301 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 4379372190 ps |
CPU time | 12.94 seconds |
Started | Jun 30 06:38:10 PM PDT 24 |
Finished | Jun 30 06:38:23 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-7f0eb459-b63a-4ed8-a677-eedaa10268f2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527965301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.1527965301 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2369460955 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 1559975630 ps |
CPU time | 2.73 seconds |
Started | Jun 30 06:38:10 PM PDT 24 |
Finished | Jun 30 06:38:13 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-f66043e2-469e-4161-8a3c-6a7d29151ed4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369460955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 369460955 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4151549111 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 2076691991 ps |
CPU time | 1.39 seconds |
Started | Jun 30 06:38:10 PM PDT 24 |
Finished | Jun 30 06:38:11 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-bfe373d5-b53a-44ac-a144-c62ff8a44f0b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151549111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.4151549111 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3165974304 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 45203043598 ps |
CPU time | 36.12 seconds |
Started | Jun 30 06:38:11 PM PDT 24 |
Finished | Jun 30 06:38:47 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-cba6ead4-4b66-40ce-8e03-e06a823070e3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165974304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.3165974304 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3147421407 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 210532750 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:38:10 PM PDT 24 |
Finished | Jun 30 06:38:11 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-403162b0-2810-4e1f-a42f-64a52e7d6724 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147421407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.3147421407 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1221223228 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 720596918 ps |
CPU time | 2.33 seconds |
Started | Jun 30 06:38:10 PM PDT 24 |
Finished | Jun 30 06:38:13 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-48bb441b-c008-4eff-8f5b-944c4968c0bd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221223228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1 221223228 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.26433432 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 85336375 ps |
CPU time | 0.76 seconds |
Started | Jun 30 06:38:16 PM PDT 24 |
Finished | Jun 30 06:38:17 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-9aff4cda-0a4c-4659-863a-e88e5b6d7d9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26433432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_parti al_access.26433432 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1710508898 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 58384435 ps |
CPU time | 0.72 seconds |
Started | Jun 30 06:38:09 PM PDT 24 |
Finished | Jun 30 06:38:10 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-ed3b1c64-b237-47e3-97b4-833434f771c0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710508898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1710508898 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1289655897 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 45900023118 ps |
CPU time | 130.84 seconds |
Started | Jun 30 06:38:08 PM PDT 24 |
Finished | Jun 30 06:40:19 PM PDT 24 |
Peak memory | 221568 kb |
Host | smart-36d2c379-21d6-40d1-b839-c177777128ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289655897 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1289655897 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.310211155 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 2019450428 ps |
CPU time | 6.12 seconds |
Started | Jun 30 06:38:09 PM PDT 24 |
Finished | Jun 30 06:38:16 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-5f74f118-9449-46b5-855c-30ae844c1805 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310211155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.310211155 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3307455579 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 2064391615 ps |
CPU time | 16.58 seconds |
Started | Jun 30 06:38:11 PM PDT 24 |
Finished | Jun 30 06:38:28 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-85ca8ff6-dd8d-40ad-ad23-ff10153d645e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307455579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3307455579 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3036820965 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1760670824 ps |
CPU time | 30.24 seconds |
Started | Jun 30 06:38:17 PM PDT 24 |
Finished | Jun 30 06:38:47 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-02b96462-23a0-49f5-8173-c7b8cce4ead5 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036820965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3036820965 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4188789725 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 5883137867 ps |
CPU time | 56.54 seconds |
Started | Jun 30 06:38:22 PM PDT 24 |
Finished | Jun 30 06:39:19 PM PDT 24 |
Peak memory | 213264 kb |
Host | smart-a162a51f-27ea-4133-a67d-3a666f352c87 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188789725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4188789725 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.90979300 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 614136263 ps |
CPU time | 2.56 seconds |
Started | Jun 30 06:38:23 PM PDT 24 |
Finished | Jun 30 06:38:26 PM PDT 24 |
Peak memory | 214268 kb |
Host | smart-36e91e23-f7d7-498b-9c5b-abc617fdcca7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90979300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.90979300 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.166844428 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 5333969446 ps |
CPU time | 11.45 seconds |
Started | Jun 30 06:38:22 PM PDT 24 |
Finished | Jun 30 06:38:34 PM PDT 24 |
Peak memory | 220844 kb |
Host | smart-8a2cf8de-6d50-490e-929a-f85167cabf82 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166844428 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.166844428 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.604976191 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 226173429 ps |
CPU time | 2.44 seconds |
Started | Jun 30 06:38:24 PM PDT 24 |
Finished | Jun 30 06:38:27 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-a9d9876a-f3b7-42bd-bd5c-334a4d60a603 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604976191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.604976191 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1207088479 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 29768218566 ps |
CPU time | 19.82 seconds |
Started | Jun 30 06:38:19 PM PDT 24 |
Finished | Jun 30 06:38:40 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-0012d577-7814-4464-8419-5be6366fedf4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207088479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1207088479 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.934138200 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 72197861139 ps |
CPU time | 69.3 seconds |
Started | Jun 30 06:38:19 PM PDT 24 |
Finished | Jun 30 06:39:29 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-aa37c67e-a514-4779-a707-7f67e7175ec3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934138200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r v_dm_jtag_dmi_csr_bit_bash.934138200 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3270686301 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 5296364676 ps |
CPU time | 5.44 seconds |
Started | Jun 30 06:38:18 PM PDT 24 |
Finished | Jun 30 06:38:23 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-430debd6-09af-4e89-a18b-c0eae0069a2c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270686301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.3270686301 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.625776294 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2908948195 ps |
CPU time | 5.54 seconds |
Started | Jun 30 06:38:19 PM PDT 24 |
Finished | Jun 30 06:38:25 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-07169e80-2c15-4fb3-8dce-4d3a787b92ce |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625776294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.625776294 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3208725290 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 645637946 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:38:15 PM PDT 24 |
Finished | Jun 30 06:38:16 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-004e878c-cb19-436d-81de-0f6ed32a6ea6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208725290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3208725290 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1137284410 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 855316732 ps |
CPU time | 1.77 seconds |
Started | Jun 30 06:38:18 PM PDT 24 |
Finished | Jun 30 06:38:20 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-0d924cb8-4344-4c99-9fc2-1f7ecb817319 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137284410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1137284410 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2493148369 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 293890210 ps |
CPU time | 1.41 seconds |
Started | Jun 30 06:38:17 PM PDT 24 |
Finished | Jun 30 06:38:19 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-81a325df-07b7-40a2-8358-87f3ad9b5cc4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493148369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2 493148369 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3977936978 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 45362027 ps |
CPU time | 0.79 seconds |
Started | Jun 30 06:38:22 PM PDT 24 |
Finished | Jun 30 06:38:23 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-1bd6d2a0-72e1-4dbc-88da-57fa6d7c376d |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977936978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.3977936978 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2388355019 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 39431963 ps |
CPU time | 0.75 seconds |
Started | Jun 30 06:38:21 PM PDT 24 |
Finished | Jun 30 06:38:23 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-d0116b82-f801-45f1-8bc4-d09f2ef8e17f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388355019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2388355019 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2286523868 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 222632486 ps |
CPU time | 4 seconds |
Started | Jun 30 06:38:22 PM PDT 24 |
Finished | Jun 30 06:38:27 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-f1ff59cd-97f3-4716-8fa6-08186e812a2c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286523868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.2286523868 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2533744522 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 317695391 ps |
CPU time | 5.07 seconds |
Started | Jun 30 06:38:21 PM PDT 24 |
Finished | Jun 30 06:38:27 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-641dbbc9-4dcf-4fa1-95ee-6f5de286df3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533744522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2533744522 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.513194215 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 1716089535 ps |
CPU time | 10.02 seconds |
Started | Jun 30 06:38:20 PM PDT 24 |
Finished | Jun 30 06:38:30 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-9af188ae-a435-4196-9431-e6271be6985f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513194215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.513194215 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1675483285 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 217285579 ps |
CPU time | 3.29 seconds |
Started | Jun 30 06:39:04 PM PDT 24 |
Finished | Jun 30 06:39:08 PM PDT 24 |
Peak memory | 221384 kb |
Host | smart-5eab9b99-7d40-4529-bff8-c7de4b88dc50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675483285 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1675483285 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2032190217 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 153447572 ps |
CPU time | 1.67 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:06 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-f4773690-c6b8-4742-9714-644b1edc4d59 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032190217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2032190217 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3224323101 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 6081090870 ps |
CPU time | 16.24 seconds |
Started | Jun 30 06:39:04 PM PDT 24 |
Finished | Jun 30 06:39:22 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-8e7f7b01-0b96-4f29-aac2-216fef34d00c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224323101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.3224323101 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2768118171 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 2150743427 ps |
CPU time | 1.63 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:05 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-e7926509-62e5-4546-ac12-4c87981425de |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768118171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2768118171 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1155170966 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 176455406 ps |
CPU time | 0.93 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:04 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-8b1518b4-3b23-4273-b9ab-b2894f1df85a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155170966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 1155170966 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.81867808 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 116583392 ps |
CPU time | 3.69 seconds |
Started | Jun 30 06:39:04 PM PDT 24 |
Finished | Jun 30 06:39:09 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-47f73892-7f41-42b8-b942-4c5fb376777f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81867808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_c sr_outstanding.81867808 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3046204253 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 95216222 ps |
CPU time | 2.25 seconds |
Started | Jun 30 06:39:09 PM PDT 24 |
Finished | Jun 30 06:39:12 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-5fd8b8fa-32b0-4084-8755-515857edec00 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046204253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3046204253 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3364349649 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 635477675 ps |
CPU time | 4.05 seconds |
Started | Jun 30 06:39:05 PM PDT 24 |
Finished | Jun 30 06:39:10 PM PDT 24 |
Peak memory | 218892 kb |
Host | smart-d842286c-625f-40e2-b992-cd8ae199f04f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364349649 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3364349649 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.680191177 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 366465612 ps |
CPU time | 2.41 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:06 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-30fd209c-5f2b-4303-bacb-103f46614c02 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680191177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.680191177 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.357207319 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 13455675274 ps |
CPU time | 36.03 seconds |
Started | Jun 30 06:39:09 PM PDT 24 |
Finished | Jun 30 06:39:46 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-64a0f491-abd1-4b8b-b7cb-fc5627657a21 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357207319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rv_dm_jtag_dmi_csr_bit_bash.357207319 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1825519434 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1520552209 ps |
CPU time | 1.98 seconds |
Started | Jun 30 06:39:07 PM PDT 24 |
Finished | Jun 30 06:39:09 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-e798a670-e088-44c4-8cf4-b51eacdf6749 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825519434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 1825519434 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.515571780 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 148724294 ps |
CPU time | 0.8 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:04 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-7a137ce7-0096-47d5-8fb1-fbf35efe43d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515571780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.515571780 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2018517914 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 456896700 ps |
CPU time | 4.33 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:13 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-db3a6a34-9a72-4f74-afe9-9ee99b1dc0c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018517914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.2018517914 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1263115483 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 152482124 ps |
CPU time | 2.9 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:07 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-efc4f0a5-8bf8-4476-86c9-700286ae5dea |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263115483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1263115483 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2666578824 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1305015438 ps |
CPU time | 8.34 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:12 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-43f51cff-230e-4ac4-b7e5-5d7b7307504f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666578824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2 666578824 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.514629013 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 4189145567 ps |
CPU time | 9.56 seconds |
Started | Jun 30 06:39:12 PM PDT 24 |
Finished | Jun 30 06:39:22 PM PDT 24 |
Peak memory | 218880 kb |
Host | smart-4c45b28a-4287-4457-a4ef-2c55076e213a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514629013 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.514629013 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2351064442 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 95802133 ps |
CPU time | 1.64 seconds |
Started | Jun 30 06:39:09 PM PDT 24 |
Finished | Jun 30 06:39:11 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-b3010217-17a4-4fcf-9990-63e515d66765 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351064442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2351064442 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1535342042 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 4619289359 ps |
CPU time | 4.91 seconds |
Started | Jun 30 06:39:04 PM PDT 24 |
Finished | Jun 30 06:39:10 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-36768248-8e21-445b-af9f-cb93306c30b4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535342042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1535342042 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2909974537 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 2331584725 ps |
CPU time | 7 seconds |
Started | Jun 30 06:39:06 PM PDT 24 |
Finished | Jun 30 06:39:14 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-bfc4eeae-d5c0-4f07-8153-20ece5308bf4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909974537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 2909974537 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3409873846 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 350410092 ps |
CPU time | 1.57 seconds |
Started | Jun 30 06:39:04 PM PDT 24 |
Finished | Jun 30 06:39:07 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-ef92f22f-e7f4-4a16-93c1-3eb026a053c7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409873846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 3409873846 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1029825616 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 1940870407 ps |
CPU time | 9 seconds |
Started | Jun 30 06:39:03 PM PDT 24 |
Finished | Jun 30 06:39:14 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-a545b776-9129-4e47-90a2-a92963d61454 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029825616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.1029825616 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.828783518 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 586851412 ps |
CPU time | 3.77 seconds |
Started | Jun 30 06:39:04 PM PDT 24 |
Finished | Jun 30 06:39:09 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-c24c7286-7b8d-44de-ab9a-274a8fa3af4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828783518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.828783518 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.357856641 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1892099411 ps |
CPU time | 12.39 seconds |
Started | Jun 30 06:39:02 PM PDT 24 |
Finished | Jun 30 06:39:15 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-c6da6871-278b-4a9a-9b35-0ac0988b6101 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357856641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.357856641 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4115795943 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 155144611 ps |
CPU time | 2.21 seconds |
Started | Jun 30 06:39:09 PM PDT 24 |
Finished | Jun 30 06:39:12 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-d37aa1ce-84c0-45ce-8585-7bd5c2c3995b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115795943 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4115795943 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.165390552 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 207726132 ps |
CPU time | 2.6 seconds |
Started | Jun 30 06:39:10 PM PDT 24 |
Finished | Jun 30 06:39:13 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-cbcd5ef9-146b-4be8-b9a5-d2a24b8dba86 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165390552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.165390552 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1943060707 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 5107239209 ps |
CPU time | 11.91 seconds |
Started | Jun 30 06:39:09 PM PDT 24 |
Finished | Jun 30 06:39:22 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-a989ad0c-c1f5-4717-9518-97937d750622 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943060707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.1943060707 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2599545493 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 3156477734 ps |
CPU time | 9.93 seconds |
Started | Jun 30 06:39:09 PM PDT 24 |
Finished | Jun 30 06:39:20 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-8c008bc4-2462-4a4f-a92d-d35efb3d1a89 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599545493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 2599545493 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1622465892 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1059987674 ps |
CPU time | 1.11 seconds |
Started | Jun 30 06:39:07 PM PDT 24 |
Finished | Jun 30 06:39:09 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-aa061ccb-ba13-40ac-90ed-4f13582ea671 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622465892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 1622465892 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2854276317 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 119181586 ps |
CPU time | 3.61 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:13 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-97dd5f1b-e7c2-4797-9068-36bf483c4fb9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854276317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2854276317 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1494252196 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 725540264 ps |
CPU time | 4.55 seconds |
Started | Jun 30 06:39:11 PM PDT 24 |
Finished | Jun 30 06:39:16 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-47a25a50-9101-4ed2-a2d5-2e2bef8eafe8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494252196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1494252196 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2864548232 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 5080921928 ps |
CPU time | 19.11 seconds |
Started | Jun 30 06:39:10 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-229716cd-be95-4392-a0ea-37f6979ef434 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864548232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2 864548232 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1371261562 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 300836921 ps |
CPU time | 2.69 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:11 PM PDT 24 |
Peak memory | 217608 kb |
Host | smart-1d6af561-5bec-48f0-a572-522f52b5c00f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371261562 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1371261562 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.383585346 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 212673979 ps |
CPU time | 1.71 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:11 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-9d8ebc0d-710d-4b4b-8927-622e9485d320 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383585346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.383585346 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.278838404 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 53203394303 ps |
CPU time | 129.68 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:41:19 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-417d1a32-21f7-44c0-9435-d611beb9e7ea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278838404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rv_dm_jtag_dmi_csr_bit_bash.278838404 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2403514847 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 9596309245 ps |
CPU time | 23.26 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:31 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-749fd72f-3298-42cd-af30-b144a189d1a5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403514847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 2403514847 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1269732755 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 1040740630 ps |
CPU time | 1.88 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:11 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-d3c3ee95-4ff0-44ae-bdf7-aaaebc5b1b4c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269732755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 1269732755 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3247919846 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 421240354 ps |
CPU time | 4.24 seconds |
Started | Jun 30 06:39:11 PM PDT 24 |
Finished | Jun 30 06:39:16 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-d159711c-1aaa-40d4-8e83-f58712d11c1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247919846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3247919846 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2273367968 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 399318289 ps |
CPU time | 4.63 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:14 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-239b2215-1972-4314-a310-ec33db1aebaa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273367968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2273367968 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2493251217 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 1619389204 ps |
CPU time | 8.98 seconds |
Started | Jun 30 06:39:08 PM PDT 24 |
Finished | Jun 30 06:39:18 PM PDT 24 |
Peak memory | 221456 kb |
Host | smart-23b2b99c-e48f-44d2-b019-8bd9eb1e1a49 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493251217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2 493251217 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2263335999 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 86307172 ps |
CPU time | 2.12 seconds |
Started | Jun 30 06:39:16 PM PDT 24 |
Finished | Jun 30 06:39:19 PM PDT 24 |
Peak memory | 217492 kb |
Host | smart-f5d3d2c8-fba8-45b4-a475-7c7db3422483 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263335999 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2263335999 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2464087143 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 135038474 ps |
CPU time | 1.69 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:18 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-6ae3a7ae-0cad-465d-abdd-3012791783cf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464087143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2464087143 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3751957564 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 20265489758 ps |
CPU time | 48.97 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:40:05 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-9f1241c5-7c42-4f64-ba67-2d849d7a94fa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751957564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.3751957564 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1142561906 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 10174965873 ps |
CPU time | 19.61 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:35 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-7cc6cb75-1f4b-4567-a035-8a2c020eb49a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142561906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 1142561906 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.988903850 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 178852350 ps |
CPU time | 0.83 seconds |
Started | Jun 30 06:39:17 PM PDT 24 |
Finished | Jun 30 06:39:18 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-d51c1fdb-939c-4836-a473-0471ea341c27 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988903850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.988903850 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3251774840 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 460687921 ps |
CPU time | 4.03 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:20 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-90b8dc2a-33b3-48a3-aaed-0e8ce5330166 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251774840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.3251774840 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2605422845 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 138500077 ps |
CPU time | 4.49 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:21 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-d6cc086f-0e34-41dd-aff4-2b98852a4a59 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605422845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2605422845 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3444582310 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 123541686 ps |
CPU time | 2.45 seconds |
Started | Jun 30 06:39:22 PM PDT 24 |
Finished | Jun 30 06:39:24 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-e47680aa-70d5-432a-942a-31123c1d052a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444582310 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3444582310 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4018551772 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 7694455491 ps |
CPU time | 9.05 seconds |
Started | Jun 30 06:39:18 PM PDT 24 |
Finished | Jun 30 06:39:27 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-f0d42445-1562-4cb9-9b42-cc3bcb8634ba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018551772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.4018551772 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.396720164 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 3122530027 ps |
CPU time | 10.13 seconds |
Started | Jun 30 06:39:15 PM PDT 24 |
Finished | Jun 30 06:39:26 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-fdf69593-d34a-400a-ae5e-647d52a6ce0e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396720164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.396720164 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2388504440 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 114200895 ps |
CPU time | 0.89 seconds |
Started | Jun 30 06:39:16 PM PDT 24 |
Finished | Jun 30 06:39:17 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-674881d2-0991-47ae-8773-d8309a95f460 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388504440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2388504440 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3203239009 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 389356631 ps |
CPU time | 6.44 seconds |
Started | Jun 30 06:39:23 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-6823c313-67ad-4e68-babf-ca4aeeacb850 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203239009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.3203239009 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3388615783 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 4466926713 ps |
CPU time | 20.62 seconds |
Started | Jun 30 06:39:17 PM PDT 24 |
Finished | Jun 30 06:39:38 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-e3b4a86d-73d8-47f0-9c4d-2102ab064479 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388615783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3 388615783 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2991948561 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 207981214 ps |
CPU time | 2.82 seconds |
Started | Jun 30 06:39:24 PM PDT 24 |
Finished | Jun 30 06:39:27 PM PDT 24 |
Peak memory | 218364 kb |
Host | smart-eccefb6e-bfb4-47df-b3d0-6bbaaea18d22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991948561 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2991948561 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.929965423 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 253310419 ps |
CPU time | 1.63 seconds |
Started | Jun 30 06:39:26 PM PDT 24 |
Finished | Jun 30 06:39:28 PM PDT 24 |
Peak memory | 213136 kb |
Host | smart-45a47608-45e5-4d55-bdd0-82a5372013b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929965423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.929965423 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1647846207 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 11554275763 ps |
CPU time | 32.66 seconds |
Started | Jun 30 06:39:21 PM PDT 24 |
Finished | Jun 30 06:39:55 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-25040bcd-7b9a-4001-b1f7-3204db42b170 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647846207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.1647846207 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1595226258 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 834286849 ps |
CPU time | 2.85 seconds |
Started | Jun 30 06:39:22 PM PDT 24 |
Finished | Jun 30 06:39:25 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-851f5655-efe4-4ac2-9276-007d77081e31 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595226258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 1595226258 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2413706620 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 762729654 ps |
CPU time | 1.15 seconds |
Started | Jun 30 06:39:23 PM PDT 24 |
Finished | Jun 30 06:39:25 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-d398e44e-96aa-4bc5-84a9-a50bbf3ebce8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413706620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2413706620 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.405698251 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 2637532769 ps |
CPU time | 5.05 seconds |
Started | Jun 30 06:39:23 PM PDT 24 |
Finished | Jun 30 06:39:28 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-4eb536a8-4d37-4418-8ccc-7e74a63ab0d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405698251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_ csr_outstanding.405698251 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.4023693453 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 193342227 ps |
CPU time | 2.38 seconds |
Started | Jun 30 06:39:25 PM PDT 24 |
Finished | Jun 30 06:39:28 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-fec25012-7855-4712-815a-70bd54aa18aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023693453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.4023693453 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.70152147 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2018938671 ps |
CPU time | 10.88 seconds |
Started | Jun 30 06:39:26 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-52b0231b-dc10-430e-ac92-bda46a539b30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70152147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.70152147 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1543573985 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 485761774 ps |
CPU time | 2.83 seconds |
Started | Jun 30 06:39:25 PM PDT 24 |
Finished | Jun 30 06:39:28 PM PDT 24 |
Peak memory | 221420 kb |
Host | smart-b2fc21d7-f032-4e06-b959-91a51d15096d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543573985 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1543573985 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2462075465 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 1316193447 ps |
CPU time | 2.69 seconds |
Started | Jun 30 06:39:22 PM PDT 24 |
Finished | Jun 30 06:39:25 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-89323760-c490-4938-8558-43452dc24823 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462075465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2462075465 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1912798034 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 34233606859 ps |
CPU time | 22.83 seconds |
Started | Jun 30 06:39:22 PM PDT 24 |
Finished | Jun 30 06:39:45 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-1b7beb8e-d1d5-46b4-bbf3-bd0925049ab5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912798034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.1912798034 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2730855041 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 8745084853 ps |
CPU time | 10.6 seconds |
Started | Jun 30 06:39:22 PM PDT 24 |
Finished | Jun 30 06:39:33 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-d83f5d5f-b1ec-444b-bb5a-3155e0cf4788 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730855041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 2730855041 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4250485654 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 545481779 ps |
CPU time | 2.18 seconds |
Started | Jun 30 06:39:24 PM PDT 24 |
Finished | Jun 30 06:39:26 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-17e991e4-04a8-4a06-aebc-106e80014278 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250485654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 4250485654 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3304014044 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 157698824 ps |
CPU time | 6.26 seconds |
Started | Jun 30 06:39:24 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-fd1023a7-7de6-4a73-9233-8efa59dbb19f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304014044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.3304014044 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1312799134 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 572184453 ps |
CPU time | 5.55 seconds |
Started | Jun 30 06:39:22 PM PDT 24 |
Finished | Jun 30 06:39:28 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-c225f96a-5df6-4d56-89bb-d3a4b01b8a2c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312799134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1312799134 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3591263355 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 1550956255 ps |
CPU time | 3.28 seconds |
Started | Jun 30 06:39:26 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 218468 kb |
Host | smart-f065041f-6e3b-482c-96ba-2a5957943a5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591263355 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3591263355 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2855220368 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 84826337 ps |
CPU time | 1.61 seconds |
Started | Jun 30 06:39:28 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-38051158-545d-4497-9b9b-005c66abbab9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855220368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2855220368 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1416401309 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 5055945993 ps |
CPU time | 3.85 seconds |
Started | Jun 30 06:39:26 PM PDT 24 |
Finished | Jun 30 06:39:31 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-98f12685-ae99-4036-92bb-a220ad54d993 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416401309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.1416401309 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2753628501 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 11482692561 ps |
CPU time | 10.59 seconds |
Started | Jun 30 06:39:21 PM PDT 24 |
Finished | Jun 30 06:39:32 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-a8c0fb54-e29c-4cb2-9f1a-a7df4317eb1e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753628501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2753628501 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1367339959 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 306950611 ps |
CPU time | 0.78 seconds |
Started | Jun 30 06:39:24 PM PDT 24 |
Finished | Jun 30 06:39:25 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-eb61a77b-2b5b-416b-9f06-fc2ed13f37b8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367339959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 1367339959 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2391809130 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 89815622 ps |
CPU time | 3.58 seconds |
Started | Jun 30 06:39:28 PM PDT 24 |
Finished | Jun 30 06:39:32 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-c8303a24-f0c1-45d6-9c32-94cc10ac50f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391809130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.2391809130 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.764225944 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 288024596 ps |
CPU time | 2.73 seconds |
Started | Jun 30 06:39:27 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-b0cd0ef9-2120-4c35-a3cc-fa1f0b972871 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764225944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.764225944 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3094569457 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 507433853 ps |
CPU time | 9.76 seconds |
Started | Jun 30 06:39:22 PM PDT 24 |
Finished | Jun 30 06:39:32 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-7ab21199-e8b5-4f11-a3e1-6da487fb60a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094569457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3 094569457 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.388843292 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 2338568088 ps |
CPU time | 28.01 seconds |
Started | Jun 30 06:38:22 PM PDT 24 |
Finished | Jun 30 06:38:51 PM PDT 24 |
Peak memory | 213252 kb |
Host | smart-1b97127c-22e5-4236-bd6c-35bd2dbb66da |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388843292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.rv_dm_csr_aliasing.388843292 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4271402904 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 5053951254 ps |
CPU time | 33.35 seconds |
Started | Jun 30 06:38:30 PM PDT 24 |
Finished | Jun 30 06:39:04 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-e0df30e9-782d-4f08-a6ec-af7e2d392b96 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271402904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4271402904 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3302642548 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 399576730 ps |
CPU time | 2.69 seconds |
Started | Jun 30 06:38:29 PM PDT 24 |
Finished | Jun 30 06:38:32 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-3eb6f672-8dab-4aae-85f3-b316c78e73d4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302642548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3302642548 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.660773275 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 347657388 ps |
CPU time | 3.72 seconds |
Started | Jun 30 06:38:27 PM PDT 24 |
Finished | Jun 30 06:38:31 PM PDT 24 |
Peak memory | 221084 kb |
Host | smart-b0b588cc-3b86-4aa0-82d2-4adb248247e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660773275 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.660773275 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2875414281 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 84860462 ps |
CPU time | 2.25 seconds |
Started | Jun 30 06:38:28 PM PDT 24 |
Finished | Jun 30 06:38:31 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-99031d5f-5246-4225-82c9-e5804204a155 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875414281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2875414281 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2350330161 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 12804791218 ps |
CPU time | 33.52 seconds |
Started | Jun 30 06:38:28 PM PDT 24 |
Finished | Jun 30 06:39:02 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-839b2174-5821-4309-bee4-c1557e4e14fc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350330161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2350330161 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2151455773 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 12040332303 ps |
CPU time | 18.28 seconds |
Started | Jun 30 06:38:29 PM PDT 24 |
Finished | Jun 30 06:38:48 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-04244d60-94ca-41ce-bbaf-54b222bf8c70 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151455773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.2151455773 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.636153246 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 1848040436 ps |
CPU time | 5.17 seconds |
Started | Jun 30 06:38:19 PM PDT 24 |
Finished | Jun 30 06:38:25 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-fef36c77-cea3-45f1-a1f4-2c717725c653 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636153246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _hw_reset.636153246 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1816260041 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 1394223172 ps |
CPU time | 1.81 seconds |
Started | Jun 30 06:38:27 PM PDT 24 |
Finished | Jun 30 06:38:29 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-0ab64cc3-7660-4bd3-a385-8c8264e65a03 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816260041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1 816260041 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1074261550 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 1713067940 ps |
CPU time | 1.94 seconds |
Started | Jun 30 06:38:23 PM PDT 24 |
Finished | Jun 30 06:38:26 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-1c30a4bf-a956-4699-98e6-e9b2a804e465 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074261550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1074261550 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3757928398 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 11880280030 ps |
CPU time | 15.23 seconds |
Started | Jun 30 06:38:24 PM PDT 24 |
Finished | Jun 30 06:38:40 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-a18b6a15-01ef-4503-b5bd-7286d75e89c3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757928398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.3757928398 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.922827566 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 1587345672 ps |
CPU time | 5.01 seconds |
Started | Jun 30 06:38:21 PM PDT 24 |
Finished | Jun 30 06:38:27 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-027e275a-011f-4b60-a066-93da7697bb3b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922827566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _hw_reset.922827566 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3170241768 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 166508028 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:38:21 PM PDT 24 |
Finished | Jun 30 06:38:22 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-4daf6067-4b04-4e83-a7c3-b87f4204510c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170241768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3 170241768 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3259589596 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 138464283 ps |
CPU time | 0.83 seconds |
Started | Jun 30 06:38:29 PM PDT 24 |
Finished | Jun 30 06:38:31 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-e87337e3-1c38-4fd7-833e-e9a04c58b691 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259589596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3259589596 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3272384120 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 314775446 ps |
CPU time | 0.71 seconds |
Started | Jun 30 06:38:28 PM PDT 24 |
Finished | Jun 30 06:38:29 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-53638461-47a8-4d0e-aae9-6aa7878753f4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272384120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3272384120 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.758522514 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 622440646 ps |
CPU time | 6.58 seconds |
Started | Jun 30 06:38:27 PM PDT 24 |
Finished | Jun 30 06:38:34 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-3d015954-502b-4460-bb02-5fbe479db44a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758522514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c sr_outstanding.758522514 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3307316911 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 266430728 ps |
CPU time | 3.14 seconds |
Started | Jun 30 06:38:27 PM PDT 24 |
Finished | Jun 30 06:38:31 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-80b0bc2e-a732-4669-a59e-d8f96c4df80a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307316911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3307316911 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2691295665 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 1745066144 ps |
CPU time | 28.81 seconds |
Started | Jun 30 06:38:33 PM PDT 24 |
Finished | Jun 30 06:39:02 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-3b64ebc5-8619-4410-aa1b-87504ac3913a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691295665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2691295665 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3816346417 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 747363304 ps |
CPU time | 2.68 seconds |
Started | Jun 30 06:38:33 PM PDT 24 |
Finished | Jun 30 06:38:36 PM PDT 24 |
Peak memory | 214260 kb |
Host | smart-2d4985cc-47da-4972-8663-6c92a188cf5b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816346417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3816346417 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.595011453 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 776144292 ps |
CPU time | 4.11 seconds |
Started | Jun 30 06:38:39 PM PDT 24 |
Finished | Jun 30 06:38:43 PM PDT 24 |
Peak memory | 221596 kb |
Host | smart-b76b74bf-5f08-4214-8e05-70801d69d96e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595011453 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.595011453 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1439438703 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 153581446 ps |
CPU time | 1.78 seconds |
Started | Jun 30 06:38:33 PM PDT 24 |
Finished | Jun 30 06:38:35 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-1965f854-f1a1-4b82-97e8-06c9dbd7d14c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439438703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1439438703 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.24421113 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 17773228283 ps |
CPU time | 29.23 seconds |
Started | Jun 30 06:38:33 PM PDT 24 |
Finished | Jun 30 06:39:03 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-d3315f82-f98b-4123-93b7-9221215d51c7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24421113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_ aliasing.24421113 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1826814203 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 23258896826 ps |
CPU time | 67.56 seconds |
Started | Jun 30 06:38:32 PM PDT 24 |
Finished | Jun 30 06:39:40 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-11230abc-8cf7-442b-8f44-f1a1a31b3ee6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826814203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.1826814203 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.137436193 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 2225190152 ps |
CPU time | 2.91 seconds |
Started | Jun 30 06:38:36 PM PDT 24 |
Finished | Jun 30 06:38:40 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-953eea54-b3ae-4522-8b36-1a04f82313e7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137436193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _hw_reset.137436193 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3600206115 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 6624395013 ps |
CPU time | 18.05 seconds |
Started | Jun 30 06:38:35 PM PDT 24 |
Finished | Jun 30 06:38:53 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-e3fe7717-8121-4a0a-9804-6689e3d8407d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600206115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3 600206115 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1978811370 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 341298115 ps |
CPU time | 1.41 seconds |
Started | Jun 30 06:38:29 PM PDT 24 |
Finished | Jun 30 06:38:31 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-f497d703-6333-4f37-bb2a-a1a1239c3940 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978811370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.1978811370 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.734643383 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 23511669143 ps |
CPU time | 54.96 seconds |
Started | Jun 30 06:38:30 PM PDT 24 |
Finished | Jun 30 06:39:25 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-c24cf017-54b5-43f2-b043-fe65da5301fb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734643383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _bit_bash.734643383 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3869244503 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 225099882 ps |
CPU time | 1.04 seconds |
Started | Jun 30 06:38:28 PM PDT 24 |
Finished | Jun 30 06:38:30 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-5896c240-e5bd-42fb-9d65-f70044ea1b91 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869244503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.3869244503 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3475601692 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 228569034 ps |
CPU time | 0.99 seconds |
Started | Jun 30 06:38:28 PM PDT 24 |
Finished | Jun 30 06:38:30 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-b5521476-5ab9-444d-b070-797cf20c2552 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475601692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3 475601692 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2855700792 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 144667838 ps |
CPU time | 0.69 seconds |
Started | Jun 30 06:38:33 PM PDT 24 |
Finished | Jun 30 06:38:34 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-f256e0c8-9d39-4d70-a941-38f31e766c31 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855700792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.2855700792 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.756553242 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 70823673 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:38:34 PM PDT 24 |
Finished | Jun 30 06:38:35 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-64e9692b-df6f-4b21-9e5d-7ed594a9682f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756553242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.756553242 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1240581446 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 1485635534 ps |
CPU time | 8.42 seconds |
Started | Jun 30 06:38:34 PM PDT 24 |
Finished | Jun 30 06:38:42 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-e05e43a8-7436-4676-9dbb-caa9749e711c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240581446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1240581446 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.444399809 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 44317199133 ps |
CPU time | 41.53 seconds |
Started | Jun 30 06:38:34 PM PDT 24 |
Finished | Jun 30 06:39:16 PM PDT 24 |
Peak memory | 221508 kb |
Host | smart-46000a38-1718-42a6-b253-1f62f816e830 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444399809 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.444399809 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4022385805 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 170786669 ps |
CPU time | 3.97 seconds |
Started | Jun 30 06:38:34 PM PDT 24 |
Finished | Jun 30 06:38:38 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-981e73a7-5660-4a3a-b53d-9a912992ee91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022385805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4022385805 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2914193481 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 3886735569 ps |
CPU time | 22.97 seconds |
Started | Jun 30 06:38:37 PM PDT 24 |
Finished | Jun 30 06:39:00 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-21d42d5b-2e92-405b-a939-ecaef85a9818 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914193481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2914193481 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.985183985 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 3278497740 ps |
CPU time | 32.43 seconds |
Started | Jun 30 06:38:40 PM PDT 24 |
Finished | Jun 30 06:39:13 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-4a287f60-13b9-4f30-9ebd-0953c4bdfa4e |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985183985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.rv_dm_csr_aliasing.985183985 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2028570246 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 10202221931 ps |
CPU time | 71.02 seconds |
Started | Jun 30 06:38:47 PM PDT 24 |
Finished | Jun 30 06:39:58 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-2cc33bce-4872-45d0-9b92-00f8e26d1fbb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028570246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2028570246 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3860398578 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 658733071 ps |
CPU time | 1.96 seconds |
Started | Jun 30 06:38:46 PM PDT 24 |
Finished | Jun 30 06:38:49 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-f1431332-3eb0-43a3-9fcf-7a1ef8ff8646 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860398578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3860398578 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3112782117 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 241442969 ps |
CPU time | 2.18 seconds |
Started | Jun 30 06:38:45 PM PDT 24 |
Finished | Jun 30 06:38:48 PM PDT 24 |
Peak memory | 221424 kb |
Host | smart-4be1ba2e-409b-49de-963b-b4e44dad9dac |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112782117 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3112782117 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.604957985 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 105491920 ps |
CPU time | 2.37 seconds |
Started | Jun 30 06:38:45 PM PDT 24 |
Finished | Jun 30 06:38:47 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-05475c3d-94e4-45f0-800c-ba0d2228bd5d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604957985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.604957985 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.472998793 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 16412598638 ps |
CPU time | 42.89 seconds |
Started | Jun 30 06:38:39 PM PDT 24 |
Finished | Jun 30 06:39:23 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-ad115f33-d432-40c7-a5df-2ac80c073469 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472998793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _aliasing.472998793 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1537720578 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 4805682264 ps |
CPU time | 14.29 seconds |
Started | Jun 30 06:38:39 PM PDT 24 |
Finished | Jun 30 06:38:54 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-92261262-fc82-4f90-83fc-b88c4a3860c5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537720578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.1537720578 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3318188220 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 22016872138 ps |
CPU time | 59.06 seconds |
Started | Jun 30 06:38:43 PM PDT 24 |
Finished | Jun 30 06:39:43 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-1ef2a483-2667-4c15-89dc-0e93cac6d09f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318188220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.3318188220 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.8464557 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 6402586090 ps |
CPU time | 5.24 seconds |
Started | Jun 30 06:38:43 PM PDT 24 |
Finished | Jun 30 06:38:49 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-e5e0a7ad-d91f-4c67-ba77-e2fc9f7cf2ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8464557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.8464557 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3306803194 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 1700063723 ps |
CPU time | 3.02 seconds |
Started | Jun 30 06:38:39 PM PDT 24 |
Finished | Jun 30 06:38:42 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-da8265b1-8570-4c37-9bcf-6c00c11f659a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306803194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.3306803194 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2002168462 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 5155246037 ps |
CPU time | 5.84 seconds |
Started | Jun 30 06:38:38 PM PDT 24 |
Finished | Jun 30 06:38:44 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-fbc4923a-b2ec-4caf-9c49-75f0384c87be |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002168462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.2002168462 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.87460604 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 666168781 ps |
CPU time | 1.03 seconds |
Started | Jun 30 06:38:40 PM PDT 24 |
Finished | Jun 30 06:38:41 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-5b778555-17d6-4c02-8092-981dcf9401bc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87460604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_ hw_reset.87460604 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1362038436 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 96590012 ps |
CPU time | 0.91 seconds |
Started | Jun 30 06:38:43 PM PDT 24 |
Finished | Jun 30 06:38:45 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-e6b529d1-11d0-45a8-9430-453f9c79ceaf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362038436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 362038436 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1094794139 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 52400263 ps |
CPU time | 0.74 seconds |
Started | Jun 30 06:38:45 PM PDT 24 |
Finished | Jun 30 06:38:46 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-9f2ee65b-4897-4830-b17e-84667dc57586 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094794139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1094794139 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3127168094 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 45078351 ps |
CPU time | 0.69 seconds |
Started | Jun 30 06:38:47 PM PDT 24 |
Finished | Jun 30 06:38:48 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-c071d08d-8db9-43aa-8d2a-5ebd7440463e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127168094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3127168094 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1962566476 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 6313180434 ps |
CPU time | 8.79 seconds |
Started | Jun 30 06:38:46 PM PDT 24 |
Finished | Jun 30 06:38:55 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-e72bacfe-90a5-4058-a200-53a65b3f0387 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962566476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1962566476 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.247272153 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 46446516551 ps |
CPU time | 42.75 seconds |
Started | Jun 30 06:38:41 PM PDT 24 |
Finished | Jun 30 06:39:24 PM PDT 24 |
Peak memory | 220988 kb |
Host | smart-b9178796-be6c-4cfa-9459-c9c9e899538d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247272153 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.247272153 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2060391062 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 184559957 ps |
CPU time | 2.14 seconds |
Started | Jun 30 06:38:44 PM PDT 24 |
Finished | Jun 30 06:38:46 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-9d2d5992-e9c0-4c92-8ae0-74958e908c48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060391062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2060391062 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3498539653 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 5689497366 ps |
CPU time | 19.33 seconds |
Started | Jun 30 06:38:46 PM PDT 24 |
Finished | Jun 30 06:39:06 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-6bbcddf8-5690-436b-ba5c-726693edbcef |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498539653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3498539653 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.189823230 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 4270313146 ps |
CPU time | 6.72 seconds |
Started | Jun 30 06:38:51 PM PDT 24 |
Finished | Jun 30 06:38:58 PM PDT 24 |
Peak memory | 217940 kb |
Host | smart-2cd3f8e1-8d06-454f-b83d-161c079436d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189823230 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.189823230 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3478727325 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 136842588 ps |
CPU time | 1.71 seconds |
Started | Jun 30 06:38:45 PM PDT 24 |
Finished | Jun 30 06:38:47 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-bd733913-07c0-4ebc-8df0-c886e9a90978 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478727325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3478727325 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2373158523 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 7997902598 ps |
CPU time | 20.93 seconds |
Started | Jun 30 06:38:47 PM PDT 24 |
Finished | Jun 30 06:39:08 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-b00cde09-f5fe-42dd-bb8b-c1106820ed26 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373158523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.2373158523 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2831362781 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 11757466039 ps |
CPU time | 10.5 seconds |
Started | Jun 30 06:38:45 PM PDT 24 |
Finished | Jun 30 06:38:56 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-f53ebdda-d57d-4c6e-a4aa-ba7985c28b0c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831362781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2 831362781 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.552852021 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 124875279 ps |
CPU time | 1.04 seconds |
Started | Jun 30 06:38:44 PM PDT 24 |
Finished | Jun 30 06:38:45 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-b7ce129b-6ae7-469d-9ea4-bb40375847ba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552852021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.552852021 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.287682664 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 5555436233 ps |
CPU time | 5.49 seconds |
Started | Jun 30 06:38:44 PM PDT 24 |
Finished | Jun 30 06:38:50 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-74311c8f-e98d-4690-bba7-3a8bf2a9e04e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287682664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c sr_outstanding.287682664 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1797645450 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 29208523725 ps |
CPU time | 24.83 seconds |
Started | Jun 30 06:38:46 PM PDT 24 |
Finished | Jun 30 06:39:12 PM PDT 24 |
Peak memory | 221196 kb |
Host | smart-5a40cde4-7b6d-480e-aa65-e2e951ab5e8f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797645450 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1797645450 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2475118404 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 324150372 ps |
CPU time | 5.2 seconds |
Started | Jun 30 06:38:46 PM PDT 24 |
Finished | Jun 30 06:38:52 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-08ebb20d-4415-4f3a-94c1-21c551f7d963 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475118404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2475118404 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2957687187 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 2414861559 ps |
CPU time | 11.15 seconds |
Started | Jun 30 06:38:44 PM PDT 24 |
Finished | Jun 30 06:38:56 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-b7685e84-4678-40e3-8006-bd30081a745c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957687187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2957687187 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2218226238 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 2074763923 ps |
CPU time | 4.81 seconds |
Started | Jun 30 06:38:51 PM PDT 24 |
Finished | Jun 30 06:38:56 PM PDT 24 |
Peak memory | 219424 kb |
Host | smart-c128c2c8-e118-4c31-ab21-95920eb8bda8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218226238 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2218226238 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.10016987 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 249255514 ps |
CPU time | 2.18 seconds |
Started | Jun 30 06:38:52 PM PDT 24 |
Finished | Jun 30 06:38:54 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-0ed11f44-f301-4200-a29e-bc8f053a078d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10016987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.10016987 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1751315408 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 18711388854 ps |
CPU time | 15.57 seconds |
Started | Jun 30 06:38:51 PM PDT 24 |
Finished | Jun 30 06:39:07 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-f449917b-1a0b-4cf0-a59d-1e6bd0d8cbb2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751315408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.1751315408 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2975095906 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 6953825278 ps |
CPU time | 17.32 seconds |
Started | Jun 30 06:38:51 PM PDT 24 |
Finished | Jun 30 06:39:09 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-6683e0d9-d5fe-44ac-8ae4-156d924c5d92 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975095906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 975095906 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3131230741 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 217193294 ps |
CPU time | 0.91 seconds |
Started | Jun 30 06:38:51 PM PDT 24 |
Finished | Jun 30 06:38:52 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-9ad7b0b5-0b2c-49fc-9870-5d1f3f057484 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131230741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3 131230741 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2159949340 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1056650173 ps |
CPU time | 4.25 seconds |
Started | Jun 30 06:38:51 PM PDT 24 |
Finished | Jun 30 06:38:56 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-e15ec57b-3e98-4b99-a5d1-b5839c11d4e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159949340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.2159949340 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1229226392 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 184971737 ps |
CPU time | 5.14 seconds |
Started | Jun 30 06:38:52 PM PDT 24 |
Finished | Jun 30 06:38:58 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-37531540-5174-4154-8121-e61dc82aa1bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229226392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1229226392 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3725107357 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 1177443827 ps |
CPU time | 3.11 seconds |
Started | Jun 30 06:38:58 PM PDT 24 |
Finished | Jun 30 06:39:02 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-b1849716-d24e-44d1-894a-32478985c4c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725107357 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3725107357 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2658644773 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 277044573 ps |
CPU time | 2.22 seconds |
Started | Jun 30 06:38:57 PM PDT 24 |
Finished | Jun 30 06:39:00 PM PDT 24 |
Peak memory | 213176 kb |
Host | smart-f930d5fd-7cdf-49e1-a266-59f6b6fbcbc3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658644773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2658644773 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1813314388 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 61612600726 ps |
CPU time | 57.92 seconds |
Started | Jun 30 06:38:58 PM PDT 24 |
Finished | Jun 30 06:39:57 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-c9da5bee-9bff-4d5a-9ef8-5d8e10ccdc84 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813314388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.1813314388 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2486914422 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1554782483 ps |
CPU time | 1.39 seconds |
Started | Jun 30 06:38:52 PM PDT 24 |
Finished | Jun 30 06:38:54 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-f6cbb1c4-6a51-42d9-818d-7a115de90380 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486914422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2 486914422 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.712463627 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 228971375 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:38:51 PM PDT 24 |
Finished | Jun 30 06:38:53 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-ca433362-b373-4a04-8a48-17ba55cfd274 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712463627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.712463627 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1341717142 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1271028365 ps |
CPU time | 7.01 seconds |
Started | Jun 30 06:39:01 PM PDT 24 |
Finished | Jun 30 06:39:08 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-f5a1d524-7ddc-4e6b-97ca-f89f0c67591b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341717142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.1341717142 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2336923931 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 5996830576 ps |
CPU time | 21.07 seconds |
Started | Jun 30 06:38:58 PM PDT 24 |
Finished | Jun 30 06:39:20 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-ca20c3b9-5d80-45a8-a8f7-6f0c3a0c5a8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336923931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2336923931 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.669060001 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 1586580493 ps |
CPU time | 3.03 seconds |
Started | Jun 30 06:38:57 PM PDT 24 |
Finished | Jun 30 06:39:01 PM PDT 24 |
Peak memory | 221408 kb |
Host | smart-7c1f3546-9745-4611-ae4c-0e5307bef73f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669060001 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.669060001 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3336488177 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 238427103 ps |
CPU time | 1.63 seconds |
Started | Jun 30 06:38:59 PM PDT 24 |
Finished | Jun 30 06:39:01 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-95128af9-c823-4969-83a8-5ef9712bdd69 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336488177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3336488177 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2698958738 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 14606853270 ps |
CPU time | 27.55 seconds |
Started | Jun 30 06:38:57 PM PDT 24 |
Finished | Jun 30 06:39:25 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-d24b722e-8978-430d-a5b5-6db9568ae590 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698958738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.2698958738 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1561073280 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 3105345137 ps |
CPU time | 8.18 seconds |
Started | Jun 30 06:38:58 PM PDT 24 |
Finished | Jun 30 06:39:06 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-526fdc69-eb6a-4f24-a504-86dbe2564691 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561073280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1 561073280 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3522962667 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 177618094 ps |
CPU time | 1.09 seconds |
Started | Jun 30 06:39:01 PM PDT 24 |
Finished | Jun 30 06:39:02 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-5f170528-f51e-4cf2-b17a-fdb6eee0ba3a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522962667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 522962667 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3506655804 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1432150058 ps |
CPU time | 7.6 seconds |
Started | Jun 30 06:38:56 PM PDT 24 |
Finished | Jun 30 06:39:04 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-91f35ebf-4b3f-48cd-ae91-5f9372a238c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506655804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.3506655804 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.269982266 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 181624419 ps |
CPU time | 5.27 seconds |
Started | Jun 30 06:38:58 PM PDT 24 |
Finished | Jun 30 06:39:04 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-c8cc9f15-55e4-440a-b355-ac058c6a0985 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269982266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.269982266 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3322636467 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 3386404167 ps |
CPU time | 18.03 seconds |
Started | Jun 30 06:38:57 PM PDT 24 |
Finished | Jun 30 06:39:16 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-3a695847-62bc-48b9-b270-dcd781fb9f3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322636467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3322636467 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3869276037 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 2941057065 ps |
CPU time | 4.96 seconds |
Started | Jun 30 06:39:05 PM PDT 24 |
Finished | Jun 30 06:39:10 PM PDT 24 |
Peak memory | 221488 kb |
Host | smart-4aeb02ad-dc8c-44dd-aab5-cd189ce85b99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869276037 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3869276037 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2129907368 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 123888610 ps |
CPU time | 2.46 seconds |
Started | Jun 30 06:39:05 PM PDT 24 |
Finished | Jun 30 06:39:08 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-ccd90a00-44a4-409c-963e-5d21101082a5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129907368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2129907368 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3972657545 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 26266948290 ps |
CPU time | 25.84 seconds |
Started | Jun 30 06:38:58 PM PDT 24 |
Finished | Jun 30 06:39:24 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-0e3a58e1-1491-44b9-916b-7fcf4f2885eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972657545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.3972657545 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4229626793 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 2367012504 ps |
CPU time | 3.65 seconds |
Started | Jun 30 06:38:57 PM PDT 24 |
Finished | Jun 30 06:39:02 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-7cd50dd1-7457-46be-9161-a55a7cd48f50 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229626793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4 229626793 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1509584124 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 280120071 ps |
CPU time | 0.98 seconds |
Started | Jun 30 06:38:58 PM PDT 24 |
Finished | Jun 30 06:39:00 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-78816c20-81fc-420d-a168-ea5b9d847017 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509584124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 509584124 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.885265518 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 288318633 ps |
CPU time | 6.46 seconds |
Started | Jun 30 06:39:06 PM PDT 24 |
Finished | Jun 30 06:39:13 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-ab128e88-c3aa-477d-83f3-e36e150790e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885265518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.885265518 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.551469852 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 489707035 ps |
CPU time | 2.92 seconds |
Started | Jun 30 06:38:57 PM PDT 24 |
Finished | Jun 30 06:39:00 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-c53cdba7-d293-412e-adc1-4cc0aee159ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551469852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.551469852 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3952898551 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 1877912535 ps |
CPU time | 11.02 seconds |
Started | Jun 30 06:38:59 PM PDT 24 |
Finished | Jun 30 06:39:10 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-c993a063-c798-46af-b16d-85e87f4591c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952898551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3952898551 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.429539299 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 211165948 ps |
CPU time | 0.83 seconds |
Started | Jun 30 06:39:36 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-25cadfea-de2b-44d3-b71e-24431b726f24 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429539299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.429539299 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1999855507 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 8839020343 ps |
CPU time | 7.13 seconds |
Started | Jun 30 06:39:29 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-2e45f58d-254c-48f4-a19d-f54c06c11164 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999855507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1999855507 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2899701192 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 4536664741 ps |
CPU time | 13.67 seconds |
Started | Jun 30 06:39:27 PM PDT 24 |
Finished | Jun 30 06:39:41 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-e2e7ff5c-98e3-433e-a802-b8200610b111 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899701192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2899701192 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2032067899 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 597014865 ps |
CPU time | 2.06 seconds |
Started | Jun 30 06:39:29 PM PDT 24 |
Finished | Jun 30 06:39:32 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-6e99e170-58a9-474b-b9f8-711d6114f53c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032067899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2032067899 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.4175507597 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 3620814714 ps |
CPU time | 5.9 seconds |
Started | Jun 30 06:39:29 PM PDT 24 |
Finished | Jun 30 06:39:36 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-fa2398a8-fd35-4ced-b204-8564d9c3aea9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175507597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4175507597 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3211762608 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 762829645 ps |
CPU time | 1.28 seconds |
Started | Jun 30 06:39:29 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-3336c676-f1a2-4ce9-83e0-0affaf059bbf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211762608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3211762608 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1355882084 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 56796416 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:36 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-c41af379-0e63-481c-914e-aa413c7adf87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355882084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1355882084 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.2441755220 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 268758426 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:39:35 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 215476 kb |
Host | smart-3bca2567-fe78-4a29-a554-4877126b29a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441755220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2441755220 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1442549768 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 3574366837 ps |
CPU time | 2.54 seconds |
Started | Jun 30 06:39:29 PM PDT 24 |
Finished | Jun 30 06:39:32 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-92d206ce-bae4-43d7-9650-fe93ade9c2c1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1442549768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.1442549768 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.127898714 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 454902208 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:39:37 PM PDT 24 |
Finished | Jun 30 06:39:39 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-4500da4a-a9a6-4d48-985d-82ff3c82cdca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=127898714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.127898714 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1767667009 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 236395245 ps |
CPU time | 1.12 seconds |
Started | Jun 30 06:39:28 PM PDT 24 |
Finished | Jun 30 06:39:30 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-1dd48840-8096-46b8-a54e-023768c3a6ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767667009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1767667009 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.822144133 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 1530326523 ps |
CPU time | 4.67 seconds |
Started | Jun 30 06:39:33 PM PDT 24 |
Finished | Jun 30 06:39:38 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-cfa427b8-e87a-4dae-a86f-a8c6dba0af85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822144133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.822144133 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2916024372 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 468406888 ps |
CPU time | 1.37 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-caac7c85-ee1b-426a-a692-e0d02f508218 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916024372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2916024372 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3650215359 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 1070601965 ps |
CPU time | 2.35 seconds |
Started | Jun 30 06:39:39 PM PDT 24 |
Finished | Jun 30 06:39:42 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-9666fbf7-308a-479e-9e78-91a39a2ffb34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650215359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3650215359 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.266481145 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 441505521 ps |
CPU time | 1.89 seconds |
Started | Jun 30 06:39:31 PM PDT 24 |
Finished | Jun 30 06:39:33 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-a7ba699d-69c9-4c20-9202-b0bc4d9d2679 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266481145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.266481145 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2213008941 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 4471290688 ps |
CPU time | 3.9 seconds |
Started | Jun 30 06:39:27 PM PDT 24 |
Finished | Jun 30 06:39:31 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-71d9d957-b8f1-434a-9666-687f202f3aa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213008941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2213008941 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.1704033761 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 254552938 ps |
CPU time | 1.37 seconds |
Started | Jun 30 06:39:40 PM PDT 24 |
Finished | Jun 30 06:39:41 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-e27d427c-b9e4-4a30-ac2b-f34ad20767d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704033761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1704033761 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2426580368 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1901404449 ps |
CPU time | 5.39 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:41 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-56699145-bbb8-4b2d-991a-7ef32a3986cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426580368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2426580368 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.575753408 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 662951231 ps |
CPU time | 2.59 seconds |
Started | Jun 30 06:39:28 PM PDT 24 |
Finished | Jun 30 06:39:31 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-ea59d4ef-4a2a-4b74-858c-d07b7e037051 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575753408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.575753408 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.3352223662 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1846372369 ps |
CPU time | 2.18 seconds |
Started | Jun 30 06:39:29 PM PDT 24 |
Finished | Jun 30 06:39:32 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-68986b22-d19b-497a-8b48-98a0ab6ffcf4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352223662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3352223662 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.2361664803 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 5176335847 ps |
CPU time | 13.19 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:48 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-1da8e21c-1770-42f4-abd2-a5d0eceebcac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361664803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2361664803 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.3747984687 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 5314663712 ps |
CPU time | 5.22 seconds |
Started | Jun 30 06:39:29 PM PDT 24 |
Finished | Jun 30 06:39:35 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-858ad40f-5ebd-4f53-84bd-ec16afbfb6d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747984687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3747984687 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.652626271 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 78715728 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:39:42 PM PDT 24 |
Finished | Jun 30 06:39:44 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-af0ee5e5-8a64-466d-a8f4-c720ae24362f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652626271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.652626271 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.3753409476 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 51585535 ps |
CPU time | 0.8 seconds |
Started | Jun 30 06:39:40 PM PDT 24 |
Finished | Jun 30 06:39:41 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-982c6725-c605-4db9-9f8f-94fdbbf298d4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753409476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3753409476 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2424899786 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3154769938 ps |
CPU time | 3.14 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-a7c3499b-fcc0-43a1-8b4c-f15444001a0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424899786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2424899786 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3724153097 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 2203513240 ps |
CPU time | 2.7 seconds |
Started | Jun 30 06:39:33 PM PDT 24 |
Finished | Jun 30 06:39:36 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-9d6a28c0-a024-4deb-b3e2-bd29e3002afc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724153097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3724153097 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2037541080 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 449484966 ps |
CPU time | 1.73 seconds |
Started | Jun 30 06:39:37 PM PDT 24 |
Finished | Jun 30 06:39:40 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-f5a07701-3f0a-4245-a449-5b6c5f628bbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2037541080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2037541080 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1161971213 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 266445646 ps |
CPU time | 0.87 seconds |
Started | Jun 30 06:39:36 PM PDT 24 |
Finished | Jun 30 06:39:38 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-5a41017f-d48c-49f2-b73d-b3c5c192f73a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161971213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1161971213 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.987608550 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 371948898 ps |
CPU time | 1.18 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:36 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-e1a693d0-edf6-4de1-857c-fe03e040cff2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987608550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.987608550 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2502491165 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 3165293598 ps |
CPU time | 9.73 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:45 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-45da92bf-d102-414d-ad2a-a92a2de424b8 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2502491165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.2502491165 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2126243725 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 532903773 ps |
CPU time | 1.25 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:44 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-c7ebe091-c4af-4999-a250-8609119813ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126243725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2126243725 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.1165484360 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 435146585 ps |
CPU time | 1.76 seconds |
Started | Jun 30 06:39:35 PM PDT 24 |
Finished | Jun 30 06:39:38 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-ea452cbb-0b0f-45f1-8627-c1101517ccfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165484360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1165484360 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3736335201 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 1163676154 ps |
CPU time | 1.05 seconds |
Started | Jun 30 06:39:44 PM PDT 24 |
Finished | Jun 30 06:39:45 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-d8942839-096f-4a44-a835-f59f06954743 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736335201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3736335201 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.217686202 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 320882198 ps |
CPU time | 1.2 seconds |
Started | Jun 30 06:39:45 PM PDT 24 |
Finished | Jun 30 06:39:47 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-89381420-c7f1-4260-a88f-79345296663b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217686202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.217686202 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3574991744 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1077694577 ps |
CPU time | 3.51 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:46 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-66bde2d8-7394-4102-bdbc-69ac9e434ce0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574991744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3574991744 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1940333371 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 149701867 ps |
CPU time | 0.79 seconds |
Started | Jun 30 06:39:43 PM PDT 24 |
Finished | Jun 30 06:39:45 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-c03854c6-2329-43eb-bbc4-b62f5a2b1912 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940333371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1940333371 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1171385252 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 1231509982 ps |
CPU time | 1.35 seconds |
Started | Jun 30 06:39:35 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-59620d07-78f2-4989-aa89-a8b7dba60cbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171385252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1171385252 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1077205469 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 2023292915 ps |
CPU time | 2.09 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:37 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-5eacd0f5-5fe0-497b-a481-a0a96bd7c5cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077205469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1077205469 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.4085185940 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 200343963 ps |
CPU time | 0.81 seconds |
Started | Jun 30 06:39:42 PM PDT 24 |
Finished | Jun 30 06:39:44 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-b4a707e5-d1e1-4f83-b45d-c39c29d1889e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085185940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4085185940 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.3173096973 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 445777490 ps |
CPU time | 1.73 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:43 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-1b84e541-8cc4-4562-8c73-506ebc189411 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173096973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3173096973 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.874056393 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 233769298 ps |
CPU time | 1.32 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:43 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-e8d240eb-8f5f-45b8-ac9f-60e67178afa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874056393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.874056393 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.2100764920 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 102461398 ps |
CPU time | 1.08 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:43 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-4c29bd04-5350-438e-8217-2b41ea97196d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100764920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2100764920 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.924836242 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 4968298806 ps |
CPU time | 8.2 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:49 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-18048012-bfb3-49fe-b0c8-7103c328b988 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=924836242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.924836242 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.1697218221 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 2666142217 ps |
CPU time | 2.95 seconds |
Started | Jun 30 06:39:32 PM PDT 24 |
Finished | Jun 30 06:39:36 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-4646e533-be5a-46dc-92ee-63b7abec8196 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697218221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1697218221 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.833144625 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 336600035 ps |
CPU time | 1.18 seconds |
Started | Jun 30 06:39:43 PM PDT 24 |
Finished | Jun 30 06:39:45 PM PDT 24 |
Peak memory | 237400 kb |
Host | smart-0787fa76-e2fb-4361-959c-b6c725865e89 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833144625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.833144625 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.3545461439 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1215301884 ps |
CPU time | 1.12 seconds |
Started | Jun 30 06:39:34 PM PDT 24 |
Finished | Jun 30 06:39:36 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-88a7ff81-3466-4edb-bf84-2bf217b9da81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545461439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3545461439 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.732179269 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 9024204909 ps |
CPU time | 9.42 seconds |
Started | Jun 30 06:39:44 PM PDT 24 |
Finished | Jun 30 06:39:54 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-39a4c111-9bb2-4e4b-8168-cb7e880d9271 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732179269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.732179269 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.2193809580 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 60117617 ps |
CPU time | 0.88 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:01 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-cc867ffc-ec6e-44df-985a-d4b4c5d98430 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193809580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2193809580 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1608713338 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 9079093996 ps |
CPU time | 25.94 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:26 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-83c17d9a-bc93-485b-9b95-99bde25a1648 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608713338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1608713338 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3967140962 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 7193652582 ps |
CPU time | 21.86 seconds |
Started | Jun 30 06:39:58 PM PDT 24 |
Finished | Jun 30 06:40:21 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-debfe75a-84f5-4e20-b23b-5c379948890e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3967140962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.3967140962 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.361021080 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 4998315787 ps |
CPU time | 14.16 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:14 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-b7450414-64f6-4ccc-981f-059cd55f5c28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361021080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.361021080 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.766673276 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 8483438497 ps |
CPU time | 21.27 seconds |
Started | Jun 30 06:39:58 PM PDT 24 |
Finished | Jun 30 06:40:21 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-7bea6ead-419c-492a-a6a3-f688fc718055 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766673276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.766673276 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1921142230 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 63480335 ps |
CPU time | 0.74 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:01 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-8d8b7c71-56a0-4951-92d9-e860c1d27d1f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921142230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1921142230 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.878597471 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1625880589 ps |
CPU time | 1.93 seconds |
Started | Jun 30 06:39:58 PM PDT 24 |
Finished | Jun 30 06:40:01 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-0872b4c6-520a-47b7-807f-bb9fca309476 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=878597471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.878597471 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1726857975 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 12995306509 ps |
CPU time | 29.79 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:30 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-da9c8632-3334-495d-b660-99ee7241cba1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1726857975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.1726857975 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.161135176 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 1161410369 ps |
CPU time | 1.79 seconds |
Started | Jun 30 06:39:58 PM PDT 24 |
Finished | Jun 30 06:40:01 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-ebad5ccf-c5c9-4faf-83aa-b650c64e23f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161135176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.161135176 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.1090805723 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 5463375776 ps |
CPU time | 15.89 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-403506a7-1b30-4adb-963c-48365b2979c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090805723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1090805723 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1838674451 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 57340223 ps |
CPU time | 0.81 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:01 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-66c25931-b21c-4aeb-a2d8-39146279a2c7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838674451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1838674451 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2994291255 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 4461091364 ps |
CPU time | 2.64 seconds |
Started | Jun 30 06:39:57 PM PDT 24 |
Finished | Jun 30 06:40:00 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-0ff2b235-6dd6-4753-b002-5db091e3a9b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2994291255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2994291255 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3942935067 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 14182966366 ps |
CPU time | 6.73 seconds |
Started | Jun 30 06:40:01 PM PDT 24 |
Finished | Jun 30 06:40:08 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-7cd8d907-d332-4483-8a98-0b9fcf40afce |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3942935067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3942935067 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.400220462 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 3624307490 ps |
CPU time | 2.3 seconds |
Started | Jun 30 06:39:59 PM PDT 24 |
Finished | Jun 30 06:40:02 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-f2ac6fd0-607f-4918-a4af-943a032c15ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400220462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.400220462 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.4184348776 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 9063225610 ps |
CPU time | 12.41 seconds |
Started | Jun 30 06:39:58 PM PDT 24 |
Finished | Jun 30 06:40:10 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-49bb5698-de87-4c91-8268-8a1c602893e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184348776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.4184348776 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.4167261938 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 65257572 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:40:07 PM PDT 24 |
Finished | Jun 30 06:40:08 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-4be67091-e100-4f1e-a4d9-cd318f6404f5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167261938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4167261938 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2925893758 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 2643378319 ps |
CPU time | 6.6 seconds |
Started | Jun 30 06:40:04 PM PDT 24 |
Finished | Jun 30 06:40:11 PM PDT 24 |
Peak memory | 215020 kb |
Host | smart-f985b0b5-3138-4523-aaf5-5cc226bc7eab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925893758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2925893758 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1950615665 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 836717067 ps |
CPU time | 1.24 seconds |
Started | Jun 30 06:40:03 PM PDT 24 |
Finished | Jun 30 06:40:04 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-b84da847-7d67-4d07-b5eb-ff5af3779636 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950615665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1950615665 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.609005986 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 5798221442 ps |
CPU time | 4.92 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-a9242870-f713-4629-84eb-cb7b9939989a |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=609005986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t l_access.609005986 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.1615385638 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 2189129043 ps |
CPU time | 4.19 seconds |
Started | Jun 30 06:39:58 PM PDT 24 |
Finished | Jun 30 06:40:04 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-cee76e6d-34da-460b-a8ba-b2ac944c4fba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615385638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1615385638 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.1118263118 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 7498916414 ps |
CPU time | 6.22 seconds |
Started | Jun 30 06:40:04 PM PDT 24 |
Finished | Jun 30 06:40:11 PM PDT 24 |
Peak memory | 214820 kb |
Host | smart-ef96105c-47cd-45b0-94f6-be97023e7b5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118263118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1118263118 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2065539013 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 59385435 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:40:04 PM PDT 24 |
Finished | Jun 30 06:40:05 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-c5365446-22dd-4c7f-b5c7-cb1d8ac2c299 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065539013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2065539013 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.425376520 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 1050714471 ps |
CPU time | 1.68 seconds |
Started | Jun 30 06:40:05 PM PDT 24 |
Finished | Jun 30 06:40:07 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-9949265e-e705-4375-9291-00df2bccc057 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425376520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.425376520 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2399974171 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 2408902081 ps |
CPU time | 3.43 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:10 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-6541fb22-7e64-43c1-af18-bdc2ced3178e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399974171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2399974171 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2397906257 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 2831429088 ps |
CPU time | 3.27 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:09 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-1bdd7fe2-1311-4264-ad96-e9595571a486 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2397906257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.2397906257 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.3767567751 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 1053799274 ps |
CPU time | 1.38 seconds |
Started | Jun 30 06:40:07 PM PDT 24 |
Finished | Jun 30 06:40:09 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-944fd64c-7765-4381-aaa0-95587f026646 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767567751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3767567751 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.185784249 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 68590425 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:40:07 PM PDT 24 |
Finished | Jun 30 06:40:08 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-be20eb7d-d4e0-4ef7-b592-52bffe6a8ad6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185784249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.185784249 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3056882595 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 122972341678 ps |
CPU time | 120.38 seconds |
Started | Jun 30 06:40:04 PM PDT 24 |
Finished | Jun 30 06:42:05 PM PDT 24 |
Peak memory | 217376 kb |
Host | smart-afe71821-a9fd-45a1-8952-0e54fe6e973a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056882595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3056882595 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1439218520 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 697425495 ps |
CPU time | 1.76 seconds |
Started | Jun 30 06:40:07 PM PDT 24 |
Finished | Jun 30 06:40:09 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-f3f2992f-6e9a-4f93-b343-efd5e0a72737 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439218520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1439218520 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.682142127 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 3877640596 ps |
CPU time | 11.94 seconds |
Started | Jun 30 06:40:08 PM PDT 24 |
Finished | Jun 30 06:40:20 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-66095a01-603a-4e63-b53f-5483af3e87cc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=682142127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t l_access.682142127 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.1136177580 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 1953345400 ps |
CPU time | 3.52 seconds |
Started | Jun 30 06:40:05 PM PDT 24 |
Finished | Jun 30 06:40:09 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-6eee3bfc-a470-44ee-83e3-13c2e9d1154e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136177580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1136177580 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.1324177382 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 54096603 ps |
CPU time | 0.71 seconds |
Started | Jun 30 06:40:04 PM PDT 24 |
Finished | Jun 30 06:40:05 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-d6ce204b-eaee-4501-bd13-52b0e76afe03 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324177382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1324177382 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3454415164 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 38791115059 ps |
CPU time | 30.04 seconds |
Started | Jun 30 06:40:07 PM PDT 24 |
Finished | Jun 30 06:40:37 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-b2b55fbb-fefb-48a1-9c79-77c4ccfa21c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454415164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3454415164 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.232174429 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 6885648715 ps |
CPU time | 8.33 seconds |
Started | Jun 30 06:40:07 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-3dfd5b27-69d1-4159-b6ca-97c37ab0aefd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=232174429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.232174429 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1509537386 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 3808346487 ps |
CPU time | 4.24 seconds |
Started | Jun 30 06:40:07 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-c2eceb98-aee6-4c8a-93a8-1eb32eed2c94 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1509537386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.1509537386 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1415294927 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 6606223606 ps |
CPU time | 9.95 seconds |
Started | Jun 30 06:40:04 PM PDT 24 |
Finished | Jun 30 06:40:14 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-fdb5731f-b6ef-4711-877d-37891bae7d2c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415294927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1415294927 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.1881716845 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 7917320896 ps |
CPU time | 6.6 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:13 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-8b35e7b4-e254-421e-985a-33fd5bb33449 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881716845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1881716845 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.154363930 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 45861041 ps |
CPU time | 0.77 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:07 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-4e0acac0-f512-464f-8802-33327361b054 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154363930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.154363930 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1685726513 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 2057806575 ps |
CPU time | 6.53 seconds |
Started | Jun 30 06:40:04 PM PDT 24 |
Finished | Jun 30 06:40:11 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-346315cf-420d-4f1d-92aa-2cd1e2534c4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685726513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1685726513 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2063476654 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 2198035490 ps |
CPU time | 2.72 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:09 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-837f7900-2ab2-4636-bceb-0ffb4f6dac67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063476654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2063476654 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3998011430 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2398770808 ps |
CPU time | 7.41 seconds |
Started | Jun 30 06:40:06 PM PDT 24 |
Finished | Jun 30 06:40:14 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-73de1533-dc71-43bf-973d-78ba0bb7aa79 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3998011430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.3998011430 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.3159886169 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 12223958744 ps |
CPU time | 14.52 seconds |
Started | Jun 30 06:40:05 PM PDT 24 |
Finished | Jun 30 06:40:20 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-1ebbe9fe-cc53-42ae-bc4d-e25475aef0c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159886169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3159886169 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.155162860 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 40851457 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-137f6a90-2939-4b8a-a84f-f27751ab0188 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155162860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.155162860 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.542565556 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 2829308293 ps |
CPU time | 3.11 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:14 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-82342dc2-27a2-4c6f-8e50-82a8f4b8fbd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542565556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.542565556 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3679306322 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 2772303610 ps |
CPU time | 3.14 seconds |
Started | Jun 30 06:40:12 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-36e51921-22ca-4947-a9c2-25760d5a9f27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679306322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3679306322 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3404791567 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 2421986693 ps |
CPU time | 7.56 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:19 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-ad62ea68-92ca-4263-81d6-b871bfcf4919 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3404791567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.3404791567 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.3933932816 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 6424429884 ps |
CPU time | 10.92 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:23 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-b54f0cf2-5a68-4584-81c4-ea9bb1d67fbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933932816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3933932816 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.1023146647 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 4337290266 ps |
CPU time | 5.25 seconds |
Started | Jun 30 06:40:10 PM PDT 24 |
Finished | Jun 30 06:40:15 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-9202313b-6494-4a5e-8c65-7c587af87545 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023146647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1023146647 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.2223896891 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 52455236 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:40:10 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-a261eae0-9933-42d6-9706-11d762b157b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223896891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2223896891 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1853325812 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 3560241850 ps |
CPU time | 1.93 seconds |
Started | Jun 30 06:40:13 PM PDT 24 |
Finished | Jun 30 06:40:15 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-1241d1d8-2067-437d-ae2e-4a8cb12b5611 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853325812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1853325812 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2000615126 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 3972683122 ps |
CPU time | 6.38 seconds |
Started | Jun 30 06:40:12 PM PDT 24 |
Finished | Jun 30 06:40:19 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-cc215f7b-6951-48b2-a284-79a9c289f44d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000615126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2000615126 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2746283460 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 1315385709 ps |
CPU time | 2.4 seconds |
Started | Jun 30 06:40:10 PM PDT 24 |
Finished | Jun 30 06:40:13 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-4b3e18b6-93b0-4454-8341-bb0510f48509 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2746283460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.2746283460 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.3206736724 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1529266855 ps |
CPU time | 2.77 seconds |
Started | Jun 30 06:40:09 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-d85e732e-8142-4092-8f92-1b9cdabad74b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206736724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3206736724 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.1860409157 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 137747636 ps |
CPU time | 0.87 seconds |
Started | Jun 30 06:39:49 PM PDT 24 |
Finished | Jun 30 06:39:51 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-d86ac9cc-bf83-488b-bd00-f0d121dec6a5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860409157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1860409157 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1252287425 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 111190076976 ps |
CPU time | 85.57 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:41:08 PM PDT 24 |
Peak memory | 218780 kb |
Host | smart-d2a9934b-4b96-4bdc-aca6-4a916a0352da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252287425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1252287425 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3580605773 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 7257381266 ps |
CPU time | 20.22 seconds |
Started | Jun 30 06:39:42 PM PDT 24 |
Finished | Jun 30 06:40:03 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-db3a9ebf-b44d-4dbb-bda7-7367151b7af9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580605773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3580605773 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3273535407 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 2382810335 ps |
CPU time | 3.02 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:45 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-b3c8e2dc-8130-4e47-825f-e8cd06cbff92 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3273535407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.3273535407 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.4012754506 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 1029271378 ps |
CPU time | 1.3 seconds |
Started | Jun 30 06:39:41 PM PDT 24 |
Finished | Jun 30 06:39:44 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-d4699c10-e6f7-443d-b044-807f90e0d01d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012754506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.4012754506 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2085500549 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 9329933366 ps |
CPU time | 25.49 seconds |
Started | Jun 30 06:39:42 PM PDT 24 |
Finished | Jun 30 06:40:08 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-ebf405a8-47af-49f4-9df7-e57840692fdd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085500549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2085500549 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.1502493344 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1594777029 ps |
CPU time | 1.39 seconds |
Started | Jun 30 06:39:48 PM PDT 24 |
Finished | Jun 30 06:39:51 PM PDT 24 |
Peak memory | 237336 kb |
Host | smart-bd547298-a2ba-4904-b449-b6dba1234da7 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502493344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1502493344 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.445872218 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 2904275774 ps |
CPU time | 4.73 seconds |
Started | Jun 30 06:39:40 PM PDT 24 |
Finished | Jun 30 06:39:45 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-d3b70b20-a570-4ea4-8a40-a6fa8431dd4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445872218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.445872218 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.2937904563 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 56172731 ps |
CPU time | 0.81 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-22cd2324-d165-4b3e-b69c-0e8a643b0db7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937904563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2937904563 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.1551459848 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 10334149075 ps |
CPU time | 8.65 seconds |
Started | Jun 30 06:40:12 PM PDT 24 |
Finished | Jun 30 06:40:21 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-67c3fb1f-f394-4dcc-95e9-c0cec3437e59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551459848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1551459848 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.2107578399 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 76332843 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:13 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-476ed49c-567c-47c6-856f-a866505b4ccc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107578399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2107578399 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.1458746329 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 5690596750 ps |
CPU time | 9.61 seconds |
Started | Jun 30 06:40:10 PM PDT 24 |
Finished | Jun 30 06:40:20 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-32235e37-deb0-4030-83f0-f2b7c1e42d55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458746329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1458746329 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.2898702175 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 96429199 ps |
CPU time | 0.74 seconds |
Started | Jun 30 06:40:09 PM PDT 24 |
Finished | Jun 30 06:40:10 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-9083fb61-4ebf-47bb-ba4a-108fee266794 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898702175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2898702175 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.3275778381 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 10608815986 ps |
CPU time | 10.38 seconds |
Started | Jun 30 06:40:09 PM PDT 24 |
Finished | Jun 30 06:40:19 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-cbce8b5b-0621-4790-af9b-cc86de3d22c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275778381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3275778381 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.567831125 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 38888853 ps |
CPU time | 0.72 seconds |
Started | Jun 30 06:40:13 PM PDT 24 |
Finished | Jun 30 06:40:14 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-fffdd4fd-cbd1-4f95-b368-14fa90f8834a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567831125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.567831125 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.739223179 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 6884521863 ps |
CPU time | 3.47 seconds |
Started | Jun 30 06:40:13 PM PDT 24 |
Finished | Jun 30 06:40:17 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-4f0164c5-4134-4c9c-891e-5e3b5053c8a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739223179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.739223179 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.3492856225 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 74519009 ps |
CPU time | 0.76 seconds |
Started | Jun 30 06:40:10 PM PDT 24 |
Finished | Jun 30 06:40:11 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-d522f6a3-6716-4322-b26e-046676555f99 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492856225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3492856225 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1686396878 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 118421447 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:40:09 PM PDT 24 |
Finished | Jun 30 06:40:11 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-dc0d4e33-841c-4ed4-8693-e769517637a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686396878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1686396878 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.2688836861 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 3460268660 ps |
CPU time | 4.58 seconds |
Started | Jun 30 06:40:12 PM PDT 24 |
Finished | Jun 30 06:40:17 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-62798f5a-e55c-4711-bb4c-967a5f0d414a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688836861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2688836861 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.4186768485 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 32099447 ps |
CPU time | 0.77 seconds |
Started | Jun 30 06:40:10 PM PDT 24 |
Finished | Jun 30 06:40:12 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-d2ecc1ac-71d1-437d-854c-3ca863a36100 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186768485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.4186768485 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.1385501112 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 13164430697 ps |
CPU time | 12.23 seconds |
Started | Jun 30 06:40:09 PM PDT 24 |
Finished | Jun 30 06:40:22 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-ee890aac-56c9-415e-8d0b-e0c639d47b22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385501112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1385501112 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.3160297074 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 111031319 ps |
CPU time | 0.75 seconds |
Started | Jun 30 06:40:09 PM PDT 24 |
Finished | Jun 30 06:40:10 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-7d727549-ab36-49a7-b458-f087d51f9a5e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160297074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3160297074 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.1979873053 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 3240432169 ps |
CPU time | 7.99 seconds |
Started | Jun 30 06:40:11 PM PDT 24 |
Finished | Jun 30 06:40:20 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-a506a5fa-45a0-4a10-a788-72aecb362e43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979873053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1979873053 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.772583865 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 144254796 ps |
CPU time | 0.83 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:18 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-2f1a43fa-febd-448f-bd0e-ace273d44efe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772583865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.772583865 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.3735359694 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 4624843357 ps |
CPU time | 7.54 seconds |
Started | Jun 30 06:40:14 PM PDT 24 |
Finished | Jun 30 06:40:22 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-a462523a-929f-419c-b28b-124eb00face3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735359694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3735359694 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.562177456 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 164467807 ps |
CPU time | 0.83 seconds |
Started | Jun 30 06:40:15 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-59a46140-b52f-4952-88da-6fbf04db83a9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562177456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.562177456 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.419283783 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 5665057429 ps |
CPU time | 16.86 seconds |
Started | Jun 30 06:40:17 PM PDT 24 |
Finished | Jun 30 06:40:34 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-83a190bd-8acf-42e8-8590-96276f99492c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419283783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.419283783 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.4007224775 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 185133308 ps |
CPU time | 0.78 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:49 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-87a6a265-16d1-4588-9546-af588cd15adc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007224775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4007224775 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2837407468 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 5158092973 ps |
CPU time | 3.34 seconds |
Started | Jun 30 06:39:49 PM PDT 24 |
Finished | Jun 30 06:39:53 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-910f0040-1b9c-4cc9-9d57-37a5bbcc5317 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2837407468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.2837407468 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.4205794394 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 380490381 ps |
CPU time | 0.83 seconds |
Started | Jun 30 06:39:48 PM PDT 24 |
Finished | Jun 30 06:39:50 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-5270613e-a7a5-445e-a91f-b4926885a142 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205794394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.4205794394 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.3838209311 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 17379447350 ps |
CPU time | 12.86 seconds |
Started | Jun 30 06:39:45 PM PDT 24 |
Finished | Jun 30 06:39:59 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-c2a84cea-e609-4fcc-800f-89fb29f6dcee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838209311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3838209311 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.2582154983 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1417645958 ps |
CPU time | 2.6 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:51 PM PDT 24 |
Peak memory | 237016 kb |
Host | smart-6d9ed020-4fbd-4507-9734-b31e719d3485 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582154983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2582154983 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.2886617126 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 5572052075 ps |
CPU time | 15.08 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:40:03 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-a48b41f4-e4fb-4301-95c3-1a3ad0a5ac4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886617126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2886617126 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.498828996 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 102616446 ps |
CPU time | 0.93 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:18 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-9c6d6956-6596-477e-b10c-45d7a1921a7c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498828996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.498828996 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.3667086458 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 120148999 ps |
CPU time | 0.75 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:17 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-0c4fc22a-6391-42a1-afbc-749e0d0915ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667086458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3667086458 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1069553591 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 3294486813 ps |
CPU time | 9.92 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:27 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-49c51f77-6b69-4ddc-9fe4-f1b8c823f47e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069553591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1069553591 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.545825260 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 37769816 ps |
CPU time | 0.77 seconds |
Started | Jun 30 06:40:15 PM PDT 24 |
Finished | Jun 30 06:40:17 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-40ff5bec-4fbc-4630-85a8-48997b74bbd9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545825260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.545825260 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.3575036134 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 87026549 ps |
CPU time | 0.73 seconds |
Started | Jun 30 06:40:18 PM PDT 24 |
Finished | Jun 30 06:40:19 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-871a67d4-927a-437c-a8c4-d5d6aed5f1f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575036134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3575036134 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.2040319082 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 2849745238 ps |
CPU time | 2.17 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:19 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-5f227457-269f-4b59-b72a-b5ece61e2fe0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040319082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2040319082 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.3070210156 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 152899062 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:18 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-0f7bf6b3-22d4-41a0-ad68-1509ec3060ae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070210156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3070210156 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.1019594878 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2363491862 ps |
CPU time | 7.04 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:24 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-dfd1eeb4-faa4-4027-87ea-58190ffa24c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019594878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1019594878 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.1889559835 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 34331916 ps |
CPU time | 0.68 seconds |
Started | Jun 30 06:40:17 PM PDT 24 |
Finished | Jun 30 06:40:19 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-ef0efbb0-74f5-43e1-9b6d-2f1a509cc806 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889559835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1889559835 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.3956947218 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 128862040 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:18 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-b4121988-4e06-46b7-8a9f-9e269a87777e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956947218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3956947218 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.1483032951 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 42070254 ps |
CPU time | 0.75 seconds |
Started | Jun 30 06:40:15 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-13645a6f-abb5-4d8b-aee3-d3fe5a17b960 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483032951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1483032951 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.1306573781 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 5421929311 ps |
CPU time | 7.65 seconds |
Started | Jun 30 06:40:20 PM PDT 24 |
Finished | Jun 30 06:40:28 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-22bdc6ad-730b-4a75-a0fb-f18aac402b4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306573781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1306573781 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.290383618 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 68072194 ps |
CPU time | 0.72 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:18 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-57784c0a-7d0d-44cd-a92e-a75f8b04aeed |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290383618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.290383618 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.955154957 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1947036253 ps |
CPU time | 6.04 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:23 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-8de40494-32ff-4f6f-872b-a623addb9d34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955154957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.955154957 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.1648632771 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 146251653 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:40:15 PM PDT 24 |
Finished | Jun 30 06:40:17 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-bbda4c2d-b388-41fd-986b-38623e21c590 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648632771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1648632771 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.1037467236 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 9205200020 ps |
CPU time | 24.79 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:41 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-f1e972f3-c191-490e-8edb-a8d6f689c074 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037467236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1037467236 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.2592029006 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 103703745 ps |
CPU time | 0.95 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:50 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-7391c6d6-be58-433a-8be2-b2f24ce55c8c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592029006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2592029006 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.126910993 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 4081211559 ps |
CPU time | 12.12 seconds |
Started | Jun 30 06:39:50 PM PDT 24 |
Finished | Jun 30 06:40:02 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-217cea5d-ae92-49da-a8e1-79365f0effe6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126910993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.126910993 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1519710171 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2849509171 ps |
CPU time | 3.33 seconds |
Started | Jun 30 06:39:48 PM PDT 24 |
Finished | Jun 30 06:39:52 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-79c9ecb0-acbc-43a6-8c10-8108c490ebfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519710171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1519710171 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2049929523 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 4226123333 ps |
CPU time | 3.95 seconds |
Started | Jun 30 06:39:46 PM PDT 24 |
Finished | Jun 30 06:39:52 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-bb3c93d4-7303-47ef-ab43-2b930ba75d54 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2049929523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.2049929523 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.938322115 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 179403887 ps |
CPU time | 0.96 seconds |
Started | Jun 30 06:39:48 PM PDT 24 |
Finished | Jun 30 06:39:50 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-4a646ae9-d628-4b0a-9cd9-88a829b7915d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938322115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.938322115 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.110986651 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 5739392914 ps |
CPU time | 4.87 seconds |
Started | Jun 30 06:39:46 PM PDT 24 |
Finished | Jun 30 06:39:53 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-0d3dd2b3-e13b-40c4-9386-74fd1e03dcf0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110986651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.110986651 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.340112575 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 584230689 ps |
CPU time | 2.76 seconds |
Started | Jun 30 06:39:46 PM PDT 24 |
Finished | Jun 30 06:39:49 PM PDT 24 |
Peak memory | 237788 kb |
Host | smart-07627b00-d02b-4a7b-8e2c-db3b095186c2 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340112575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.340112575 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.1339263961 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 7141725154 ps |
CPU time | 18.22 seconds |
Started | Jun 30 06:39:49 PM PDT 24 |
Finished | Jun 30 06:40:08 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-c19e6510-ce4f-4ee9-907e-02ccbdcaf03a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339263961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1339263961 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.2530028026 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 152333958 ps |
CPU time | 0.76 seconds |
Started | Jun 30 06:40:17 PM PDT 24 |
Finished | Jun 30 06:40:18 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-23f4af36-dcac-4041-81ba-39ad0d0e3153 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530028026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2530028026 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.3119139265 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 163057005 ps |
CPU time | 0.76 seconds |
Started | Jun 30 06:40:16 PM PDT 24 |
Finished | Jun 30 06:40:18 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-260921cd-3b52-4f09-a39f-d5755d6727c5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119139265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3119139265 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.2143016023 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 58019769 ps |
CPU time | 0.74 seconds |
Started | Jun 30 06:40:22 PM PDT 24 |
Finished | Jun 30 06:40:23 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-d13ca1ca-7bf6-4c3d-9e52-d9286db5f8d9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143016023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2143016023 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.240505037 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 31743199 ps |
CPU time | 0.76 seconds |
Started | Jun 30 06:40:21 PM PDT 24 |
Finished | Jun 30 06:40:22 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-169dd29b-877f-4801-b177-ed7bac36f811 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240505037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.240505037 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.961261156 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 5601078250 ps |
CPU time | 15.53 seconds |
Started | Jun 30 06:40:22 PM PDT 24 |
Finished | Jun 30 06:40:38 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-1e1910a3-f2c7-4bf9-adef-ccbded29b7aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961261156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.961261156 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.3253035855 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 54748346 ps |
CPU time | 0.82 seconds |
Started | Jun 30 06:40:22 PM PDT 24 |
Finished | Jun 30 06:40:23 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-fa2969c5-3216-4720-a760-6d1dc74c908b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253035855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3253035855 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.915453196 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 3247712506 ps |
CPU time | 10.53 seconds |
Started | Jun 30 06:40:24 PM PDT 24 |
Finished | Jun 30 06:40:35 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-c265e78c-215a-43f5-87ba-a2513be6e188 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915453196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.915453196 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.3057410337 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 150083318 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:40:20 PM PDT 24 |
Finished | Jun 30 06:40:22 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-035bd573-488f-43d8-b78f-05cdd2dcd1a1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057410337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3057410337 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.3196415597 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 3047960368 ps |
CPU time | 9.74 seconds |
Started | Jun 30 06:40:20 PM PDT 24 |
Finished | Jun 30 06:40:31 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-f5d0b30f-f140-47de-be13-66767a281897 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196415597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3196415597 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3900098512 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 46954676 ps |
CPU time | 0.79 seconds |
Started | Jun 30 06:40:24 PM PDT 24 |
Finished | Jun 30 06:40:25 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-053505ec-7655-4278-8666-2ace557d9347 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900098512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3900098512 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.1242132543 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 2637006049 ps |
CPU time | 4.44 seconds |
Started | Jun 30 06:40:22 PM PDT 24 |
Finished | Jun 30 06:40:27 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-2860b382-1ee9-4e6a-9cce-5d5e280b1df4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242132543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1242132543 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.4208842555 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 207992766 ps |
CPU time | 0.79 seconds |
Started | Jun 30 06:40:25 PM PDT 24 |
Finished | Jun 30 06:40:26 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-d8ae885c-e918-4ca5-8bb3-d1eb9c8eeed8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208842555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.4208842555 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.1138141016 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 8886071873 ps |
CPU time | 23.89 seconds |
Started | Jun 30 06:40:22 PM PDT 24 |
Finished | Jun 30 06:40:47 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-0cce264d-7468-489b-af3d-ad29735c8dad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138141016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1138141016 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.721371659 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 276696651 ps |
CPU time | 0.72 seconds |
Started | Jun 30 06:40:22 PM PDT 24 |
Finished | Jun 30 06:40:23 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-889ec47d-8735-4ab5-a89a-291130f716cb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721371659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.721371659 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.417066664 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 6543547533 ps |
CPU time | 6.98 seconds |
Started | Jun 30 06:40:21 PM PDT 24 |
Finished | Jun 30 06:40:29 PM PDT 24 |
Peak memory | 214780 kb |
Host | smart-097598df-e7f2-4a89-a554-adb7caf2742f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417066664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.417066664 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.2400006451 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 82633134 ps |
CPU time | 0.75 seconds |
Started | Jun 30 06:40:21 PM PDT 24 |
Finished | Jun 30 06:40:23 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-b198452c-f1ce-4008-be34-18aba16f1798 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400006451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2400006451 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.131400701 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 8661005694 ps |
CPU time | 5.28 seconds |
Started | Jun 30 06:40:20 PM PDT 24 |
Finished | Jun 30 06:40:26 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-3c38623b-3c42-4e30-a557-a90aad45b5d9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131400701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.131400701 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.2784593693 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 95094181 ps |
CPU time | 0.72 seconds |
Started | Jun 30 06:39:46 PM PDT 24 |
Finished | Jun 30 06:39:47 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-5e90edd2-da07-435a-b1c3-599ca9e38da7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784593693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2784593693 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3862411354 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 6178980902 ps |
CPU time | 5.38 seconds |
Started | Jun 30 06:39:49 PM PDT 24 |
Finished | Jun 30 06:39:55 PM PDT 24 |
Peak memory | 215204 kb |
Host | smart-0d058bc5-6a3c-4a74-9315-f31a7678c416 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862411354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3862411354 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.434968136 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 3878098233 ps |
CPU time | 12.37 seconds |
Started | Jun 30 06:39:48 PM PDT 24 |
Finished | Jun 30 06:40:01 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-4d4e6a91-fb82-4138-94cc-fd3126cabbea |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=434968136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl _access.434968136 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.2034102594 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1872831197 ps |
CPU time | 4.04 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:53 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-d5775ab2-9383-495d-a6f6-964e130ae589 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034102594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2034102594 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.4246825670 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 4183314547 ps |
CPU time | 4.13 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:53 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-d78d2577-4ec1-4ba0-9c7a-4bf3b414717d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246825670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.4246825670 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3064152319 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 164600895 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:49 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-033b580d-1b05-4f4a-b90e-1dde9211dbbd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064152319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3064152319 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1226466774 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 6284263538 ps |
CPU time | 18.41 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:40:07 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-10ae378f-3571-47bd-a95f-aa76eae76afc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226466774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1226466774 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2608036241 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 4836798395 ps |
CPU time | 6.98 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:56 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-3fe3fc20-6eda-461a-8c09-7aca120403fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608036241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2608036241 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1139119958 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 601015737 ps |
CPU time | 2.55 seconds |
Started | Jun 30 06:39:47 PM PDT 24 |
Finished | Jun 30 06:39:51 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-bce7929d-7a23-4062-8dd7-9f24cbda7cd0 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1139119958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.1139119958 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2438048916 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 1443906548 ps |
CPU time | 4.72 seconds |
Started | Jun 30 06:39:48 PM PDT 24 |
Finished | Jun 30 06:39:54 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-a56e2f48-9488-45f4-a1c8-f51f41b6ae74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438048916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2438048916 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.618134084 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 5568442033 ps |
CPU time | 9.69 seconds |
Started | Jun 30 06:39:49 PM PDT 24 |
Finished | Jun 30 06:40:00 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-89cbc076-ef2f-489e-9898-6107e11309a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618134084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.618134084 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1111888468 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 179292752618 ps |
CPU time | 477 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:47:51 PM PDT 24 |
Peak memory | 233080 kb |
Host | smart-1d567048-1397-48fc-aee9-2c2c77658d37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111888468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1111888468 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1116996138 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 2197555043 ps |
CPU time | 4.29 seconds |
Started | Jun 30 06:39:51 PM PDT 24 |
Finished | Jun 30 06:39:56 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-328d1fd7-79ce-4de0-9b5c-a1fac38c5c53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116996138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1116996138 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1518724248 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 10212293780 ps |
CPU time | 15.13 seconds |
Started | Jun 30 06:39:49 PM PDT 24 |
Finished | Jun 30 06:40:05 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-9d8d72cf-5cce-47b1-ae6c-6f98e9a81566 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1518724248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.1518724248 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.3472360011 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 2361983982 ps |
CPU time | 2.28 seconds |
Started | Jun 30 06:39:46 PM PDT 24 |
Finished | Jun 30 06:39:50 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-485b3b7b-786f-4862-aff3-6ae3006fc2ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472360011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3472360011 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.2802301550 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 7377226809 ps |
CPU time | 5.79 seconds |
Started | Jun 30 06:39:52 PM PDT 24 |
Finished | Jun 30 06:39:59 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-0156d7b6-95c9-4231-b6a5-d608b794795d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802301550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2802301550 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.148020319 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 102644959 ps |
CPU time | 0.74 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:39:54 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-7fccd525-e338-4801-8876-67478eb4ca90 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148020319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.148020319 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2987453453 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 67301831332 ps |
CPU time | 137.18 seconds |
Started | Jun 30 06:39:55 PM PDT 24 |
Finished | Jun 30 06:42:13 PM PDT 24 |
Peak memory | 215720 kb |
Host | smart-4c3d1ea7-7e0a-45c8-bd9e-56b83dc6783d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987453453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2987453453 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.972179255 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 4814285044 ps |
CPU time | 2.01 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:39:56 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-644788f8-e7d4-4829-a7dd-9d519dffeaa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=972179255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.972179255 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1326268209 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 1027006820 ps |
CPU time | 2.37 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:39:56 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-05ea7e9c-3cfe-4d97-b1fd-c5db641ef230 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1326268209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.1326268209 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.576051491 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 5518948548 ps |
CPU time | 2.98 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:39:57 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-a3d8a330-72f5-4da3-8c37-ce3e0d2b9afc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576051491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.576051491 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.3542348247 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 133384829 ps |
CPU time | 0.81 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:39:55 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-83b2414a-9b67-436b-a9a4-bdbb749c8be8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542348247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3542348247 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2653143236 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 16947543004 ps |
CPU time | 23.28 seconds |
Started | Jun 30 06:39:52 PM PDT 24 |
Finished | Jun 30 06:40:16 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-daae6b2f-e076-48e0-b894-afe89edf91df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653143236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2653143236 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1645248046 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 1267002312 ps |
CPU time | 4.24 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:39:58 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-0c35a73e-561f-4675-96dc-f65c9223af37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645248046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1645248046 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1602239491 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 11124775420 ps |
CPU time | 30.5 seconds |
Started | Jun 30 06:39:54 PM PDT 24 |
Finished | Jun 30 06:40:25 PM PDT 24 |
Peak memory | 213116 kb |
Host | smart-b98f9eb2-9752-4b18-80c4-a4954b2bdd82 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1602239491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.1602239491 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.400053539 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 2398093580 ps |
CPU time | 7.39 seconds |
Started | Jun 30 06:39:55 PM PDT 24 |
Finished | Jun 30 06:40:02 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-d2e7f6a5-08d3-4c8b-b4df-b352722a3765 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400053539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.400053539 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.1436218956 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 6376138430 ps |
CPU time | 8.26 seconds |
Started | Jun 30 06:39:53 PM PDT 24 |
Finished | Jun 30 06:40:02 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-f07be8d3-ed83-49fa-a111-8f171644deec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436218956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1436218956 |
Directory | /workspace/9.rv_dm_stress_all/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |