Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.20 95.27 79.59 89.42 74.36 85.50 98.21 53.09


Total tests in report: 442
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
56.15 56.15 86.66 86.66 55.31 55.31 34.99 34.99 50.00 50.00 67.83 67.83 93.17 93.17 5.11 5.11 /workspace/coverage/default/15.rv_dm_stress_all.508177890
65.70 9.55 90.13 3.47 64.83 9.52 70.02 35.03 60.26 10.26 74.00 6.17 94.74 1.58 5.94 0.83 /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1645504022
71.65 5.94 90.23 0.10 68.69 3.86 72.93 2.91 60.26 0.00 74.67 0.67 95.79 1.05 38.95 33.02 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.238528369
74.85 3.20 91.94 1.71 72.28 3.59 79.66 6.73 66.67 6.41 78.17 3.50 95.79 0.00 39.43 0.48 /workspace/coverage/default/35.rv_dm_stress_all.4045251016
76.50 1.65 91.94 0.00 72.69 0.41 79.66 0.00 73.08 6.41 78.50 0.33 95.79 0.00 43.82 4.39 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2203675164
77.57 1.07 92.04 0.10 74.48 1.79 81.42 1.76 73.08 0.00 79.17 0.67 96.00 0.21 46.79 2.97 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.125164318
78.25 0.68 92.04 0.00 75.17 0.69 84.62 3.20 73.08 0.00 79.83 0.67 96.00 0.00 47.03 0.24 /workspace/coverage/default/36.rv_dm_stress_all.1683313089
78.73 0.48 92.50 0.45 76.14 0.97 85.56 0.94 73.08 0.00 80.33 0.50 96.00 0.00 47.51 0.48 /workspace/coverage/default/7.rv_dm_alert_test.4083734609
79.16 0.43 92.50 0.00 76.14 0.00 88.06 2.50 73.08 0.00 80.33 0.00 96.00 0.00 47.98 0.48 /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.983462254
79.57 0.41 92.80 0.30 76.83 0.69 88.06 0.00 74.36 1.28 80.83 0.50 96.11 0.11 47.98 0.00 /workspace/coverage/default/1.rv_dm_debug_disabled.2415427979
79.89 0.32 93.30 0.50 77.52 0.69 88.19 0.12 74.36 0.00 81.67 0.83 96.11 0.00 48.10 0.12 /workspace/coverage/default/1.rv_dm_cmderr_exception.1900378660
80.20 0.31 93.91 0.60 77.93 0.41 88.19 0.00 74.36 0.00 82.33 0.67 96.11 0.00 48.57 0.48 /workspace/coverage/default/40.rv_dm_stress_all.702942156
80.46 0.26 94.16 0.25 78.07 0.14 88.93 0.74 74.36 0.00 83.00 0.67 96.11 0.00 48.57 0.00 /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2557283929
80.70 0.25 94.16 0.00 78.07 0.00 88.93 0.00 74.36 0.00 83.00 0.00 97.48 1.37 48.93 0.36 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2351677948
80.85 0.15 94.26 0.10 78.21 0.14 89.01 0.08 74.36 0.00 83.50 0.50 97.48 0.00 49.17 0.24 /workspace/coverage/default/0.rv_dm_rom_read_access.1075925439
80.99 0.13 94.26 0.00 78.62 0.41 89.17 0.16 74.36 0.00 83.50 0.00 97.58 0.11 49.41 0.24 /workspace/coverage/default/0.rv_dm_sec_cm.1719506702
81.11 0.13 94.41 0.15 79.03 0.41 89.17 0.00 74.36 0.00 83.83 0.33 97.58 0.00 49.41 0.00 /workspace/coverage/default/0.rv_dm_progbuf_busy.2768777125
81.23 0.12 94.41 0.00 79.03 0.00 89.42 0.25 74.36 0.00 83.83 0.00 97.58 0.00 50.00 0.59 /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1795563939
81.35 0.12 94.61 0.20 79.31 0.28 89.42 0.00 74.36 0.00 84.17 0.33 97.58 0.00 50.00 0.00 /workspace/coverage/default/32.rv_dm_stress_all.3951917213
81.46 0.11 94.91 0.30 79.31 0.00 89.42 0.00 74.36 0.00 84.67 0.50 97.58 0.00 50.00 0.00 /workspace/coverage/default/0.rv_dm_abstractcmd_status.2032262087
81.55 0.08 94.91 0.00 79.31 0.00 89.42 0.00 74.36 0.00 84.67 0.00 97.58 0.00 50.59 0.59 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.420923835
81.63 0.08 95.02 0.10 79.31 0.00 89.42 0.00 74.36 0.00 85.00 0.33 97.58 0.00 50.71 0.12 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.4156115799
81.69 0.07 95.17 0.15 79.45 0.14 89.42 0.00 74.36 0.00 85.17 0.17 97.58 0.00 50.71 0.00 /workspace/coverage/default/1.rv_dm_cmderr_busy.2551520776
81.76 0.06 95.22 0.05 79.45 0.00 89.42 0.00 74.36 0.00 85.33 0.17 97.58 0.00 50.95 0.24 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2238250420
81.81 0.05 95.22 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.33 0.00 97.58 0.00 51.31 0.36 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3487993
81.86 0.05 95.22 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.33 0.00 97.58 0.00 51.66 0.36 /workspace/coverage/default/24.rv_dm_stress_all.1107452006
81.91 0.05 95.22 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.33 0.00 97.58 0.00 52.02 0.36 /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1261471915
81.94 0.03 95.22 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.33 0.00 97.58 0.00 52.26 0.24 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.869941843
81.98 0.03 95.22 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.33 0.00 97.58 0.00 52.49 0.24 /workspace/coverage/default/8.rv_dm_stress_all.3377133469
82.01 0.03 95.27 0.05 79.45 0.00 89.42 0.00 74.36 0.00 85.50 0.17 97.58 0.00 52.49 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1153418391
82.04 0.03 95.27 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.50 0.00 97.79 0.21 52.49 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2039750011
82.07 0.03 95.27 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.50 0.00 98.00 0.21 52.49 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4116632263
82.10 0.03 95.27 0.00 79.45 0.00 89.42 0.00 74.36 0.00 85.50 0.00 98.21 0.21 52.49 0.00 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1348237737
82.12 0.02 95.27 0.00 79.59 0.14 89.42 0.00 74.36 0.00 85.50 0.00 98.21 0.00 52.49 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2073410015
82.14 0.02 95.27 0.00 79.59 0.00 89.42 0.00 74.36 0.00 85.50 0.00 98.21 0.00 52.61 0.12 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1148338277
82.15 0.02 95.27 0.00 79.59 0.00 89.42 0.00 74.36 0.00 85.50 0.00 98.21 0.00 52.73 0.12 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1660149303
82.17 0.02 95.27 0.00 79.59 0.00 89.42 0.00 74.36 0.00 85.50 0.00 98.21 0.00 52.85 0.12 /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.898056758
82.19 0.02 95.27 0.00 79.59 0.00 89.42 0.00 74.36 0.00 85.50 0.00 98.21 0.00 52.97 0.12 /workspace/coverage/default/19.rv_dm_sba_tl_access.1688607407
82.20 0.02 95.27 0.00 79.59 0.00 89.42 0.00 74.36 0.00 85.50 0.00 98.21 0.00 53.09 0.12 /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1113027576

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2926956475
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2589695190
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1363965709
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1030736978
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3787671715
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1251568501
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1527965301
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2369460955
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4151549111
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3165974304
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3147421407
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1221223228
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.26433432
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1710508898
/workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1289655897
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.310211155
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3307455579
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3036820965
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4188789725
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.90979300
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.166844428
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.604976191
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1207088479
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.934138200
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3270686301
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.625776294
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3208725290
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1137284410
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2493148369
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3977936978
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2388355019
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2286523868
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2533744522
/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.513194215
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1675483285
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2032190217
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3224323101
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2768118171
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1155170966
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.81867808
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3046204253
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3364349649
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.680191177
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.357207319
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1825519434
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.515571780
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2018517914
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1263115483
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2666578824
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.514629013
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2351064442
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1535342042
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2909974537
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3409873846
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1029825616
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.828783518
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.357856641
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4115795943
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.165390552
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1943060707
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2599545493
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1622465892
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2854276317
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1494252196
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2864548232
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1371261562
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.383585346
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.278838404
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2403514847
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1269732755
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3247919846
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2273367968
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2493251217
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2263335999
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2464087143
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3751957564
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1142561906
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.988903850
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3251774840
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2605422845
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3444582310
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4018551772
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.396720164
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2388504440
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3203239009
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3388615783
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2991948561
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.929965423
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1647846207
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1595226258
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2413706620
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.405698251
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.4023693453
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.70152147
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1543573985
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2462075465
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1912798034
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2730855041
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4250485654
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3304014044
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1312799134
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3591263355
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2855220368
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1416401309
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2753628501
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1367339959
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2391809130
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.764225944
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3094569457
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.388843292
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4271402904
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3302642548
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.660773275
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2875414281
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2350330161
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2151455773
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.636153246
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1816260041
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1074261550
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3757928398
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.922827566
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3170241768
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3259589596
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3272384120
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.758522514
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3307316911
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2691295665
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3816346417
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.595011453
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1439438703
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.24421113
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1826814203
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.137436193
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3600206115
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1978811370
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.734643383
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3869244503
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3475601692
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2855700792
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.756553242
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1240581446
/workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.444399809
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4022385805
/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2914193481
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.985183985
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Total test records in report: 442
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.rv_dm_sba_tl_access.400053539 Jun 30 06:39:55 PM PDT 24 Jun 30 06:40:02 PM PDT 24 2398093580 ps
T2 /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.609005986 Jun 30 06:40:06 PM PDT 24 Jun 30 06:40:12 PM PDT 24 5798221442 ps
T3 /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2557283929 Jun 30 06:39:59 PM PDT 24 Jun 30 06:40:06 PM PDT 24 3266461920 ps
T49 /workspace/coverage/default/12.rv_dm_sba_tl_access.400220462 Jun 30 06:39:59 PM PDT 24 Jun 30 06:40:02 PM PDT 24 3624307490 ps
T50 /workspace/coverage/default/1.rv_dm_sba_tl_access.1697218221 Jun 30 06:39:32 PM PDT 24 Jun 30 06:39:36 PM PDT 24 2666142217 ps
T4 /workspace/coverage/default/15.rv_dm_stress_all.508177890 Jun 30 06:40:06 PM PDT 24 Jun 30 06:40:13 PM PDT 24 9517560457 ps
T35 /workspace/coverage/default/7.rv_dm_alert_test.4083734609 Jun 30 06:39:52 PM PDT 24 Jun 30 06:39:54 PM PDT 24 96475665 ps
T36 /workspace/coverage/default/17.rv_dm_sba_tl_access.3159886169 Jun 30 06:40:05 PM PDT 24 Jun 30 06:40:20 PM PDT 24 12223958744 ps
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T220 /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1111888468 Jun 30 06:39:53 PM PDT 24 Jun 30 06:47:51 PM PDT 24 179292752618 ps
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T88 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.125164318 Jun 30 06:39:06 PM PDT 24 Jun 30 06:39:18 PM PDT 24 1779536061 ps
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T95 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3203239009 Jun 30 06:39:23 PM PDT 24 Jun 30 06:39:30 PM PDT 24 389356631 ps
T305 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.515571780 Jun 30 06:39:03 PM PDT 24 Jun 30 06:39:04 PM PDT 24 148724294 ps
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T106 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.137436193 Jun 30 06:38:36 PM PDT 24 Jun 30 06:38:40 PM PDT 24 2225190152 ps
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