Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	218910	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	581321	1		T4	10		T38	80		T5	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	502440	1		T4	7		T38	80		T33	1
values[0x0]	145730	1		T4	5		T5	17		T6	7
values[0x1]	152061	1		T4	8		T5	17		T6	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	166308	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	633923	1		T4	13		T38	80		T5	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2812	1		T60	1		T16	1		T167	1
valid_sources[0x01]	3376	1		T5	2		T6	2		T23	1
valid_sources[0x02]	3140	1		T15	1		T16	1		T137	1
valid_sources[0x03]	2934	1		T168	2		T72	14		T73	40
valid_sources[0x04]	2999	1		T23	5		T19	1		T72	22
valid_sources[0x05]	3726	1		T56	1		T148	2		T168	2
valid_sources[0x06]	3196	1		T61	2		T56	2		T57	1
valid_sources[0x07]	2877	1		T148	1		T169	1		T75	25
valid_sources[0x08]	3420	1		T16	1		T152	1		T72	45
valid_sources[0x09]	3563	1		T5	2		T170	1		T171	1
valid_sources[0x0a]	2637	1		T36	1		T60	2		T152	1
valid_sources[0x0b]	3270	1		T56	1		T15	1		T72	29
valid_sources[0x0c]	2881	1		T16	1		T75	6		T72	14
valid_sources[0x0d]	3230	1		T35	3		T15	1		T75	4
valid_sources[0x0e]	3207	1		T5	1		T15	1		T16	1
valid_sources[0x0f]	2658	1		T38	2		T72	23		T73	48
valid_sources[0x10]	3451	1		T5	1		T8	1		T148	1
valid_sources[0x11]	2781	1		T38	3		T5	1		T23	2
valid_sources[0x12]	3348	1		T60	2		T75	25		T72	14
valid_sources[0x13]	3424	1		T15	1		T60	1		T16	1
valid_sources[0x14]	3154	1		T6	1		T75	29		T72	21
valid_sources[0x15]	3231	1		T38	1		T15	1		T75	27
valid_sources[0x16]	3039	1		T23	1		T167	3		T72	31
valid_sources[0x17]	3183	1		T38	1		T56	1		T21	13
valid_sources[0x18]	2978	1		T152	1		T75	27		T72	19
valid_sources[0x19]	3021	1		T152	1		T151	2		T75	55
valid_sources[0x1a]	2941	1		T16	2		T75	51		T72	13
valid_sources[0x1b]	3007	1		T75	62		T72	36		T73	44
valid_sources[0x1c]	2805	1		T5	1		T17	1		T72	15
valid_sources[0x1d]	2710	1		T56	1		T22	1		T75	15
valid_sources[0x1e]	2719	1		T5	1		T35	1		T15	1
valid_sources[0x1f]	3476	1		T16	1		T22	1		T72	24
valid_sources[0x20]	2583	1		T38	1		T22	1		T75	2
valid_sources[0x21]	2845	1		T172	2		T72	6		T73	41
valid_sources[0x22]	2689	1		T6	2		T16	1		T72	33
valid_sources[0x23]	2900	1		T38	1		T11	1		T72	19
valid_sources[0x24]	3000	1		T140	1		T147	25		T72	13
valid_sources[0x25]	3068	1		T33	2		T56	1		T15	1
valid_sources[0x26]	3289	1		T18	5		T56	1		T15	1
valid_sources[0x27]	3004	1		T56	1		T72	34		T73	53
valid_sources[0x28]	3455	1		T38	1		T149	4		T173	1
valid_sources[0x29]	3700	1		T174	1		T72	62		T73	58
valid_sources[0x2a]	3019	1		T60	1		T16	1		T72	11
valid_sources[0x2b]	3481	1		T38	1		T167	1		T143	4
valid_sources[0x2c]	2882	1		T16	1		T172	1		T75	4
valid_sources[0x2d]	3434	1		T17	1		T16	1		T72	21
valid_sources[0x2e]	3324	1		T38	1		T5	1		T56	1
valid_sources[0x2f]	3332	1		T17	1		T57	3		T169	1
valid_sources[0x30]	3727	1		T38	1		T56	1		T175	5
valid_sources[0x31]	3450	1		T5	1		T56	1		T22	1
valid_sources[0x32]	2849	1		T176	15		T167	2		T72	17
valid_sources[0x33]	3067	1		T5	2		T168	1		T177	1
valid_sources[0x34]	3628	1		T9	1		T56	1		T177	3
valid_sources[0x35]	2938	1		T75	15		T72	9		T73	32
valid_sources[0x36]	2980	1		T5	1		T60	2		T171	1
valid_sources[0x37]	3343	1		T38	4		T17	3		T167	1
valid_sources[0x38]	2846	1		T38	1		T152	1		T171	1
valid_sources[0x39]	2956	1		T75	7		T72	24		T73	49
valid_sources[0x3a]	3417	1		T38	2		T56	1		T17	1
valid_sources[0x3b]	3122	1		T5	1		T60	1		T75	9
valid_sources[0x3c]	3255	1		T56	1		T167	1		T27	28
valid_sources[0x3d]	3108	1		T38	1		T148	3		T152	1
valid_sources[0x3e]	3300	1		T148	1		T172	1		T167	1
valid_sources[0x3f]	3349	1		T56	3		T60	2		T75	8
valid_sources[0x40]	2868	1		T56	1		T75	14		T72	29
valid_sources[0x41]	3304	1		T38	1		T16	1		T148	1
valid_sources[0x42]	3346	1		T167	2		T143	1		T72	21
valid_sources[0x43]	3096	1		T5	1		T56	1		T15	1
valid_sources[0x44]	2804	1		T38	1		T6	3		T56	1
valid_sources[0x45]	3257	1		T17	1		T11	1		T75	8
valid_sources[0x46]	3176	1		T38	1		T43	1		T16	1
valid_sources[0x47]	2892	1		T38	2		T56	2		T10	34
valid_sources[0x48]	3318	1		T38	2		T149	4		T172	1
valid_sources[0x49]	3315	1		T75	21		T72	22		T73	42
valid_sources[0x4a]	4735	1		T137	1		T75	11		T72	26
valid_sources[0x4b]	2986	1		T167	1		T75	25		T72	21
valid_sources[0x4c]	3222	1		T169	1		T134	1		T75	13
valid_sources[0x4d]	2832	1		T56	2		T16	1		T57	1
valid_sources[0x4e]	3028	1		T75	13		T72	49		T73	35
valid_sources[0x4f]	2773	1		T75	7		T72	11		T73	49
valid_sources[0x50]	3136	1		T167	1		T173	1		T75	8
valid_sources[0x51]	3070	1		T15	1		T152	3		T72	31
valid_sources[0x52]	3436	1		T172	4		T72	29		T73	45
valid_sources[0x53]	2875	1		T143	2		T72	22		T73	43
valid_sources[0x54]	3204	1		T56	1		T60	1		T178	2
valid_sources[0x55]	3139	1		T5	2		T36	2		T178	1
valid_sources[0x56]	3421	1		T56	1		T75	7		T72	28
valid_sources[0x57]	3001	1		T167	1		T137	1		T75	53
valid_sources[0x58]	2778	1		T6	1		T56	1		T15	1
valid_sources[0x59]	2924	1		T15	1		T16	1		T72	46
valid_sources[0x5a]	3242	1		T5	2		T15	1		T59	28
valid_sources[0x5b]	3115	1		T34	1		T9	1		T56	1
valid_sources[0x5c]	2862	1		T38	1		T16	1		T149	5
valid_sources[0x5d]	3043	1		T17	1		T16	1		T178	1
valid_sources[0x5e]	3213	1		T167	1		T75	47		T72	13
valid_sources[0x5f]	2859	1		T75	36		T72	13		T73	48
valid_sources[0x60]	2900	1		T60	1		T75	32		T72	28
valid_sources[0x61]	3340	1		T16	1		T178	1		T72	21
valid_sources[0x62]	3360	1		T5	1		T72	25		T73	50
valid_sources[0x63]	3023	1		T60	1		T136	16		T72	9
valid_sources[0x64]	3187	1		T16	1		T22	2		T75	28
valid_sources[0x65]	3057	1		T148	2		T152	2		T75	37
valid_sources[0x66]	3124	1		T16	1		T170	2		T148	1
valid_sources[0x67]	3167	1		T149	6		T75	31		T72	31
valid_sources[0x68]	2811	1		T16	1		T179	1		T75	4
valid_sources[0x69]	3012	1		T8	4		T16	1		T72	17
valid_sources[0x6a]	3110	1		T6	1		T140	1		T56	2
valid_sources[0x6b]	3066	1		T38	3		T56	1		T60	1
valid_sources[0x6c]	2619	1		T36	2		T56	1		T169	1
valid_sources[0x6d]	2780	1		T151	1		T177	1		T75	10
valid_sources[0x6e]	3168	1		T172	1		T75	1		T72	22
valid_sources[0x6f]	2871	1		T5	2		T167	1		T171	2
valid_sources[0x70]	3154	1		T38	4		T60	2		T72	37
valid_sources[0x71]	2910	1		T5	1		T16	2		T75	11
valid_sources[0x72]	2966	1		T56	3		T178	1		T75	3
valid_sources[0x73]	2803	1		T25	2		T173	1		T72	9
valid_sources[0x74]	2989	1		T72	20		T73	39		T74	20
valid_sources[0x75]	3070	1		T56	1		T17	1		T60	1
valid_sources[0x76]	3332	1		T38	2		T56	1		T72	22
valid_sources[0x77]	4088	1		T6	3		T16	2		T137	6
valid_sources[0x78]	3339	1		T38	1		T173	2		T72	24
valid_sources[0x79]	3155	1		T38	1		T56	1		T151	2
valid_sources[0x7a]	3135	1		T38	2		T5	1		T35	1
valid_sources[0x7b]	4475	1		T56	1		T60	1		T143	1
valid_sources[0x7c]	3329	1		T16	1		T57	1		T167	1
valid_sources[0x7d]	2874	1		T17	1		T167	1		T75	9
valid_sources[0x7e]	2955	1		T171	1		T75	38		T72	8
valid_sources[0x7f]	2903	1		T152	3		T75	45		T72	10
valid_sources[0x80]	3285	1		T18	1		T56	1		T171	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

294938

1

T4

1

T38

80

T35

6

values[0x0]

all_enables

biggest_size

143490

1

T4

4

T5

4

T6

3

values[0x1]

all_enables

biggest_size

142893

1

T4

5

T5

1

T6

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5123	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	22897	1		T1	1		T2	6		T4	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10453	1		T75	14		T72	34		T73	75
values[0x0]	8627	1		T1	1		T2	2		T54	1
values[0x1]	8940	1		T2	4		T54	2		T4	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3912	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	24108	1		T1	1		T2	6		T4	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	83	1		T40	1		T180	1		T181	1
valid_sources[0x01]	62	1		T89	1		T133	1		T83	5
valid_sources[0x02]	129	1		T59	1		T182	7		T83	6
valid_sources[0x03]	109	1		T183	2		T184	4		T72	1
valid_sources[0x04]	89	1		T132	1		T60	8		T183	1
valid_sources[0x05]	77	1		T185	3		T186	1		T83	5
valid_sources[0x06]	102	1		T37	1		T187	1		T72	1
valid_sources[0x07]	92	1		T42	1		T27	1		T83	1
valid_sources[0x08]	70	1		T188	1		T149	1		T91	6
valid_sources[0x09]	114	1		T189	1		T174	1		T190	2
valid_sources[0x0a]	98	1		T52	1		T66	1		T27	1
valid_sources[0x0b]	65	1		T17	1		T136	1		T83	2
valid_sources[0x0c]	109	1		T36	6		T191	2		T93	1
valid_sources[0x0d]	110	1		T180	1		T192	1		T193	2
valid_sources[0x0e]	73	1		T187	1		T83	7		T86	1
valid_sources[0x0f]	116	1		T83	6		T86	1		T99	2
valid_sources[0x10]	102	1		T17	1		T194	5		T195	14
valid_sources[0x11]	83	1		T23	1		T72	2		T92	3
valid_sources[0x12]	116	1		T28	1		T44	1		T136	4
valid_sources[0x13]	227	1		T144	2		T83	4		T85	1
valid_sources[0x14]	97	1		T83	4		T91	2		T99	5
valid_sources[0x15]	96	1		T54	1		T72	1		T73	3
valid_sources[0x16]	75	1		T196	1		T197	3		T198	1
valid_sources[0x17]	72	1		T173	1		T151	1		T74	1
valid_sources[0x18]	134	1		T170	1		T199	6		T200	2
valid_sources[0x19]	130	1		T201	2		T202	1		T203	1
valid_sources[0x1a]	98	1		T39	1		T181	1		T72	1
valid_sources[0x1b]	108	1		T204	1		T205	1		T206	1
valid_sources[0x1c]	121	1		T205	1		T134	1		T73	18
valid_sources[0x1d]	109	1		T4	1		T142	1		T207	4
valid_sources[0x1e]	99	1		T9	1		T59	1		T208	1
valid_sources[0x1f]	84	1		T205	1		T138	1		T86	2
valid_sources[0x20]	87	1		T83	1		T99	7		T92	1
valid_sources[0x21]	55	1		T209	2		T83	1		T85	1
valid_sources[0x22]	82	1		T83	2		T85	2		T99	5
valid_sources[0x23]	67	1		T72	2		T83	1		T85	1
valid_sources[0x24]	87	1		T210	4		T206	1		T83	5
valid_sources[0x25]	84	1		T132	1		T211	3		T212	1
valid_sources[0x26]	68	1		T187	1		T73	3		T83	6
valid_sources[0x27]	71	1		T213	1		T10	1		T187	1
valid_sources[0x28]	95	1		T48	1		T181	2		T144	2
valid_sources[0x29]	127	1		T133	1		T214	4		T74	3
valid_sources[0x2a]	134	1		T181	1		T183	1		T21	1
valid_sources[0x2b]	67	1		T88	1		T86	2		T91	3
valid_sources[0x2c]	75	1		T215	1		T180	1		T152	6
valid_sources[0x2d]	119	1		T145	1		T62	1		T216	1
valid_sources[0x2e]	67	1		T83	1		T99	4		T92	3
valid_sources[0x2f]	90	1		T217	1		T74	1		T85	1
valid_sources[0x30]	110	1		T37	1		T192	1		T74	2
valid_sources[0x31]	78	1		T83	3		T84	3		T86	1
valid_sources[0x32]	95	1		T37	1		T49	3		T183	1
valid_sources[0x33]	102	1		T39	1		T15	6		T218	8
valid_sources[0x34]	81	1		T219	1		T220	2		T85	1
valid_sources[0x35]	101	1		T151	1		T83	1		T84	3
valid_sources[0x36]	62	1		T190	1		T99	4		T92	1
valid_sources[0x37]	111	1		T221	18		T86	1		T85	2
valid_sources[0x38]	84	1		T17	1		T83	1		T86	1
valid_sources[0x39]	86	1		T74	1		T83	3		T91	3
valid_sources[0x3a]	108	1		T140	1		T213	2		T149	1
valid_sources[0x3b]	132	1		T18	1		T193	2		T74	2
valid_sources[0x3c]	218	1		T54	1		T39	1		T77	1
valid_sources[0x3d]	59	1		T189	1		T59	1		T213	2
valid_sources[0x3e]	54	1		T102	1		T94	3		T161	1
valid_sources[0x3f]	91	1		T205	1		T97	9		T99	8
valid_sources[0x40]	146	1		T4	1		T183	1		T192	1
valid_sources[0x41]	96	1		T155	1		T73	11		T83	3
valid_sources[0x42]	97	1		T132	1		T59	1		T153	1
valid_sources[0x43]	89	1		T9	2		T222	1		T86	4
valid_sources[0x44]	60	1		T223	7		T224	4		T85	2
valid_sources[0x45]	224	1		T225	1		T83	10		T86	1
valid_sources[0x46]	110	1		T149	1		T85	3		T99	11
valid_sources[0x47]	117	1		T171	1		T83	5		T91	1
valid_sources[0x48]	123	1		T73	3		T85	1		T99	6
valid_sources[0x49]	98	1		T153	1		T220	1		T74	2
valid_sources[0x4a]	155	1		T83	1		T99	7		T94	1
valid_sources[0x4b]	102	1		T87	1		T148	1		T183	1
valid_sources[0x4c]	74	1		T83	1		T91	1		T99	6
valid_sources[0x4d]	66	1		T99	2		T102	2		T94	2
valid_sources[0x4e]	93	1		T190	1		T83	9		T92	3
valid_sources[0x4f]	189	1		T183	1		T21	1		T222	1
valid_sources[0x50]	99	1		T10	1		T194	6		T83	6
valid_sources[0x51]	104	1		T192	1		T72	1		T83	2
valid_sources[0x52]	101	1		T57	1		T191	1		T134	1
valid_sources[0x53]	104	1		T226	3		T83	7		T86	1
valid_sources[0x54]	92	1		T37	1		T227	21		T228	1
valid_sources[0x55]	77	1		T181	2		T192	2		T83	2
valid_sources[0x56]	182	1		T28	1		T86	2		T85	1
valid_sources[0x57]	117	1		T83	4		T86	1		T85	1
valid_sources[0x58]	104	1		T42	1		T229	1		T230	1
valid_sources[0x59]	56	1		T46	4		T231	1		T83	1
valid_sources[0x5a]	102	1		T148	1		T86	2		T85	1
valid_sources[0x5b]	81	1		T132	1		T88	1		T72	1
valid_sources[0x5c]	181	1		T13	1		T99	13		T67	93
valid_sources[0x5d]	139	1		T151	1		T86	1		T99	2
valid_sources[0x5e]	77	1		T74	3		T83	1		T86	1
valid_sources[0x5f]	83	1		T232	1		T171	1		T99	3
valid_sources[0x60]	102	1		T12	2		T74	2		T83	5
valid_sources[0x61]	88	1		T233	1		T234	9		T73	7
valid_sources[0x62]	90	1		T83	2		T97	6		T99	2
valid_sources[0x63]	124	1		T133	1		T190	1		T73	3
valid_sources[0x64]	88	1		T153	1		T72	2		T83	1
valid_sources[0x65]	75	1		T83	3		T86	1		T85	1
valid_sources[0x66]	72	1		T49	2		T74	1		T83	4
valid_sources[0x67]	87	1		T235	1		T19	1		T203	1
valid_sources[0x68]	102	1		T27	1		T83	1		T99	3
valid_sources[0x69]	102	1		T149	1		T134	1		T217	1
valid_sources[0x6a]	63	1		T59	1		T154	1		T74	1
valid_sources[0x6b]	68	1		T236	1		T184	1		T229	1
valid_sources[0x6c]	113	1		T49	2		T180	2		T74	1
valid_sources[0x6d]	77	1		T26	2		T237	1		T238	1
valid_sources[0x6e]	93	1		T153	1		T75	11		T72	3
valid_sources[0x6f]	78	1		T239	1		T240	2		T27	1
valid_sources[0x70]	70	1		T31	1		T86	1		T99	4
valid_sources[0x71]	139	1		T54	1		T213	1		T241	1
valid_sources[0x72]	63	1		T83	2		T91	2		T99	6
valid_sources[0x73]	86	1		T46	3		T242	1		T91	3
valid_sources[0x74]	99	1		T145	1		T83	1		T86	1
valid_sources[0x75]	107	1		T59	1		T208	4		T21	1
valid_sources[0x76]	80	1		T37	1		T40	1		T175	1
valid_sources[0x77]	135	1		T90	13		T142	1		T222	1
valid_sources[0x78]	133	1		T37	1		T243	1		T244	2
valid_sources[0x79]	104	1		T229	1		T83	1		T86	1
valid_sources[0x7a]	470	1		T9	2		T244	1		T229	1
valid_sources[0x7b]	81	1		T205	1		T26	2		T133	1
valid_sources[0x7c]	97	1		T56	1		T206	4		T83	1
valid_sources[0x7d]	304	1		T176	1		T143	2		T83	2
valid_sources[0x7e]	122	1		T37	1		T32	6		T49	1
valid_sources[0x7f]	85	1		T152	1		T183	1		T192	1
valid_sources[0x80]	96	1		T180	1		T194	1		T85	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7438

1

T75

14

T72

15

T73

28

values[0x0]

all_enables

biggest_size

7815

1

T1

1

T2

2

T4

3

values[0x1]

all_enables

biggest_size

7644

1

T2

4

T4

3

T37

2