SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 831664 | 1 | T4 | 20 | T5 | 34 | T6 | 14 | |||
auto[1] | 25864 | 1 | T38 | 80 | T56 | 80 | T72 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 857334 | 1 | T4 | 20 | T38 | 80 | T5 | 34 | |||
values[1] | 19 | 1 | T73 | 1 | T84 | 1 | T91 | 2 | |||
values[2] | 8 | 1 | T91 | 1 | T161 | 1 | T164 | 1 | |||
values[3] | 108 | 1 | T72 | 5 | T73 | 6 | T74 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 857316 | 1 | T4 | 20 | T38 | 80 | T5 | 34 | |||
values[1] | 25 | 1 | T72 | 1 | T73 | 1 | T86 | 1 | |||
values[2] | 2 | 1 | T72 | 1 | T86 | 1 | - | - | |||
values[3] | 103 | 1 | T72 | 2 | T73 | 6 | T74 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 857228 | 1 | T4 | 20 | T38 | 80 | T5 | 34 | |||
auto[TlIntgErrCmd] | 88 | 1 | T72 | 2 | T73 | 6 | T74 | 4 | |||
auto[TlIntgErrData] | 106 | 1 | T72 | 5 | T73 | 7 | T74 | 3 | |||
auto[TlIntgErrBoth] | 106 | 1 | T72 | 3 | T73 | 7 | T74 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 53462 | 0 | T1 | 1 | T2 | 6 | T54 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53254 | 1 | T1 | 1 | T2 | 6 | T54 | 3 | |||
values[1] | 18 | 1 | T73 | 2 | T84 | 1 | T86 | 2 | |||
values[2] | 5 | 1 | T86 | 2 | T161 | 1 | T165 | 1 | |||
values[3] | 118 | 1 | T72 | 3 | T73 | 7 | T74 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53264 | 1 | T1 | 1 | T2 | 6 | T54 | 3 | |||
values[1] | 34 | 1 | T72 | 3 | T74 | 4 | T84 | 1 | |||
values[2] | 8 | 1 | T72 | 1 | T159 | 2 | T164 | 2 | |||
values[3] | 91 | 1 | T72 | 4 | T73 | 2 | T74 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 53162 | 1 | T1 | 1 | T2 | 6 | T54 | 3 | |||
auto[TlIntgErrCmd] | 102 | 1 | T73 | 10 | T74 | 3 | T84 | 5 | |||
auto[TlIntgErrData] | 92 | 1 | T72 | 7 | T73 | 2 | T74 | 4 | |||
auto[TlIntgErrBoth] | 106 | 1 | T72 | 3 | T73 | 8 | T74 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |