Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	274021	1		T4	10		T5	29		T6	9
full_word	583507	1		T4	10		T38	80		T5	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	857228	1		T4	20		T38	80		T5	34
auto[TlIntgErrCmd]	88	1		T72	2		T73	6		T74	4
auto[TlIntgErrData]	106	1		T72	5		T73	7		T74	3
auto[TlIntgErrBoth]	106	1		T72	3		T73	7		T74	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	504959	1		T4	7		T38	80		T33	1
auto[1]	352569	1		T4	13		T5	34		T6	14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	209644	1		T4	6		T33	1		T35	4
auto[TlIntgErrNone]	partial	auto[1]	64098	1		T4	4		T5	29		T6	9
auto[TlIntgErrNone]	full_word	auto[0]	295171	1		T4	1		T38	80		T35	6
auto[TlIntgErrNone]	full_word	auto[1]	288315	1		T4	9		T5	5		T6	5
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T72	1		T73	2		T74	3
auto[TlIntgErrCmd]	partial	auto[1]	38	1		T72	1		T73	4		T74	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T159	1		T160	1		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1		T72	5		T73	3		T74	2
auto[TlIntgErrData]	partial	auto[1]	46	1		T73	3		T74	1		T86	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T91	2		T161	1		T162	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T73	1		T91	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T72	2		T74	1		T86	4
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T72	1		T73	7		T74	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T84	1		T86	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T86	1		T91	1		T163	1