Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.12 96.97 59.57 91.58 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 117207184 19608 0 0
late_debug_enable_rd_A 117207184 2038 0 0
late_debug_enable_regwen_rd_A 117207184 1426 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117207184 19608 0 0
T67 966190 528 0 0
T72 126037 4 0 0
T73 270477 1 0 0
T74 57113 2 0 0
T83 12692 717 0 0
T84 67026 1 0 0
T85 27668 137 0 0
T86 143612 7 0 0
T91 313201 6 0 0
T92 133549 171 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117207184 2038 0 0
T67 966190 86 0 0
T84 67026 41 0 0
T95 28115 32 0 0
T97 22103 45 0 0
T98 16559 5 0 0
T101 7091 3 0 0
T103 48694 79 0 0
T104 366423 218 0 0
T105 9438 111 0 0
T109 12566 6 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117207184 1426 0 0
T67 966190 82 0 0
T84 67026 44 0 0
T95 28115 45 0 0
T97 22103 16 0 0
T98 16559 3 0 0
T101 7091 7 0 0
T103 48694 37 0 0
T104 366423 209 0 0
T105 9438 147 0 0
T109 12566 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%