Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	54606035	6303195	0	0
MemTLResponseWithoutDebugIsError_A	54606035	13	0	0
NdmResetAckNeedsDebug_A	54606035	0	0	0
SbaTLRequestNeedsDebug_A	54606035	14018	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54606035	6303195	0	0
T4	67772	16548	0	0
T5	0	358233	0	0
T6	0	183814	0	0
T7	18776	0	0	0
T8	0	11023	0	0
T9	0	135905	0	0
T13	170190	0	0	0
T14	32021	0	0	0
T18	0	35639	0	0
T23	0	37257	0	0
T33	0	25385	0	0
T35	0	12741	0	0
T36	0	53795	0	0
T37	4283	0	0	0
T38	2537	0	0	0
T39	6991	0	0	0
T40	1691	0	0	0
T41	270373	0	0	0
T42	11396	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54606035	13	0	0
T23	229303	0	0	0
T32	504211	0	0	0
T35	24601	0	0	0
T36	186577	0	0	0
T43	2165	12	0	0
T44	0	1	0	0
T45	112362	0	0	0
T46	1662	0	0	0
T47	17844	0	0	0
T48	3713	0	0	0
T49	3995	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54606035	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54606035	14018	0	0
T2	580298	14	0	0
T3	7559	0	0	0
T4	67772	0	0	0
T13	170190	42	0	0
T14	32021	8	0	0
T28	0	1758	0	0
T29	0	5	0	0
T37	4283	0	0	0
T38	2537	0	0	0
T39	6991	0	0	0
T40	1691	0	0	0
T41	0	123	0	0
T50	0	154	0	0
T51	0	116	0	0
T52	0	97	0	0
T53	0	110	0	0
T54	2444	0	0	0