Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9361890 9360560 0 0
selKnown1 61266269 61264935 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9361890 9360560 0 0
T1 2334 2332 0 0
T2 19385 19381 0 0
T3 3990 3986 0 0
T4 20950 20946 0 0
T5 0 18 0 0
T6 0 24 0 0
T8 0 22 0 0
T13 11083 11079 0 0
T14 2 0 0 0
T28 0 8 0 0
T30 0 18 0 0
T33 0 6 0 0
T37 382 378 0 0
T38 644 640 0 0
T39 367 363 0 0
T40 906 902 0 0
T54 361 357 0 0
T66 0 6 0 0
T71 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 61266269 61264935 0 0
T1 40872 40870 0 0
T2 589996 589992 0 0
T3 9565 9561 0 0
T4 78251 78247 0 0
T5 0 8 0 0
T6 0 6 0 0
T8 0 8 0 0
T9 0 6 0 0
T13 175732 175728 0 0
T14 2 0 0 0
T28 0 8 0 0
T33 0 6 0 0
T37 4475 4471 0 0
T38 2860 2856 0 0
T39 7175 7171 0 0
T40 2145 2141 0 0
T54 2625 2621 0 0
T71 0 4 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2700915 2700692 0 0
selKnown1 54606035 54605810 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2700915 2700692 0 0
T1 1167 1166 0 0
T2 9686 9685 0 0
T3 1984 1983 0 0
T4 10471 10470 0 0
T13 5540 5539 0 0
T37 190 189 0 0
T38 321 320 0 0
T39 182 181 0 0
T40 452 451 0 0
T54 179 178 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 54606035 54605810 0 0
T1 39705 39704 0 0
T2 580298 580297 0 0
T3 7559 7558 0 0
T4 67772 67771 0 0
T13 170190 170189 0 0
T37 4283 4282 0 0
T38 2537 2536 0 0
T39 6991 6990 0 0
T40 1691 1690 0 0
T54 2444 2443 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 760 537 0 0
selKnown1 609 384 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 760 537 0 0
T2 6 5 0 0
T3 11 10 0 0
T4 4 3 0 0
T5 0 6 0 0
T6 0 12 0 0
T8 0 11 0 0
T13 1 0 0 0
T14 1 0 0 0
T28 0 4 0 0
T30 0 9 0 0
T33 0 3 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T54 1 0 0 0
T71 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 609 384 0 0
T2 6 5 0 0
T3 11 10 0 0
T4 4 3 0 0
T5 0 4 0 0
T6 0 3 0 0
T8 0 4 0 0
T9 0 3 0 0
T13 1 0 0 0
T14 1 0 0 0
T28 0 4 0 0
T33 0 3 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T54 1 0 0 0
T71 0 2 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6658201 6657758 0 0
selKnown1 6657995 6657554 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6658201 6657758 0 0
T1 1167 1166 0 0
T2 9687 9686 0 0
T3 1984 1983 0 0
T4 10471 10470 0 0
T13 5541 5540 0 0
T37 190 189 0 0
T38 321 320 0 0
T39 183 182 0 0
T40 452 451 0 0
T54 180 179 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6657995 6657554 0 0
T1 1167 1166 0 0
T2 9686 9685 0 0
T3 1984 1983 0 0
T4 10471 10470 0 0
T13 5540 5539 0 0
T37 190 189 0 0
T38 321 320 0 0
T39 182 181 0 0
T40 452 451 0 0
T54 179 178 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2014 1573 0 0
selKnown1 1630 1187 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2014 1573 0 0
T2 6 5 0 0
T3 11 10 0 0
T4 4 3 0 0
T5 0 12 0 0
T6 0 12 0 0
T8 0 11 0 0
T13 1 0 0 0
T14 1 0 0 0
T28 0 4 0 0
T30 0 9 0 0
T33 0 3 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T54 1 0 0 0
T66 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1630 1187 0 0
T2 6 5 0 0
T3 11 10 0 0
T4 4 3 0 0
T5 0 4 0 0
T6 0 3 0 0
T8 0 4 0 0
T9 0 3 0 0
T13 1 0 0 0
T14 1 0 0 0
T28 0 4 0 0
T33 0 3 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T54 1 0 0 0
T71 0 2 0 0

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