Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199363	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	548159	1		T7	4		T8	11		T9	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	460461	1		T7	6		T8	7		T4	8
values[0x0]	138812	1		T7	5		T8	14		T9	4
values[0x1]	148249	1		T7	3		T8	13		T9	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150149	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	597373	1		T7	6		T8	13		T9	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2700	1		T165	2		T143	1		T58	15
valid_sources[0x01]	2592	1		T58	12		T72	3		T71	12
valid_sources[0x02]	2953	1		T58	6		T72	2		T71	9
valid_sources[0x03]	3364	1		T166	4		T52	2		T15	1
valid_sources[0x04]	2644	1		T141	1		T58	11		T70	2
valid_sources[0x05]	2779	1		T15	2		T58	15		T71	14
valid_sources[0x06]	3414	1		T58	7		T70	9		T72	2
valid_sources[0x07]	3417	1		T144	4		T148	5		T14	1
valid_sources[0x08]	3297	1		T36	2		T58	12		T70	6
valid_sources[0x09]	2691	1		T52	1		T23	1		T11	1
valid_sources[0x0a]	2800	1		T149	2		T58	11		T70	1
valid_sources[0x0b]	2675	1		T153	2		T58	10		T70	1
valid_sources[0x0c]	2996	1		T53	4		T147	6		T58	10
valid_sources[0x0d]	3135	1		T52	2		T146	1		T58	12
valid_sources[0x0e]	2932	1		T58	8		T70	2		T71	13
valid_sources[0x0f]	3310	1		T52	1		T58	13		T70	3
valid_sources[0x10]	3150	1		T152	1		T53	4		T58	10
valid_sources[0x11]	3530	1		T52	1		T151	8		T58	10
valid_sources[0x12]	2513	1		T15	1		T140	4		T58	12
valid_sources[0x13]	2633	1		T23	2		T149	1		T58	5
valid_sources[0x14]	2997	1		T26	1		T58	12		T70	8
valid_sources[0x15]	2711	1		T26	1		T58	14		T70	6
valid_sources[0x16]	3070	1		T7	2		T140	2		T24	2
valid_sources[0x17]	2698	1		T9	2		T16	1		T146	1
valid_sources[0x18]	2769	1		T36	1		T16	1		T58	9
valid_sources[0x19]	3392	1		T141	1		T58	6		T72	3
valid_sources[0x1a]	3288	1		T52	2		T18	3		T58	12
valid_sources[0x1b]	3148	1		T26	1		T150	1		T58	4
valid_sources[0x1c]	2862	1		T144	2		T15	1		T140	2
valid_sources[0x1d]	2848	1		T36	2		T35	1		T143	1
valid_sources[0x1e]	2543	1		T36	1		T146	1		T141	1
valid_sources[0x1f]	2710	1		T152	1		T154	1		T58	6
valid_sources[0x20]	2875	1		T152	1		T143	1		T154	1
valid_sources[0x21]	3409	1		T52	3		T23	2		T58	13
valid_sources[0x22]	2725	1		T19	1		T58	9		T70	6
valid_sources[0x23]	2910	1		T7	1		T58	11		T72	1
valid_sources[0x24]	2435	1		T23	1		T143	1		T141	1
valid_sources[0x25]	3477	1		T16	1		T58	13		T70	4
valid_sources[0x26]	3446	1		T16	1		T14	1		T58	10
valid_sources[0x27]	2608	1		T26	1		T52	1		T23	2
valid_sources[0x28]	3113	1		T149	1		T53	2		T150	3
valid_sources[0x29]	3008	1		T58	10		T70	4		T72	4
valid_sources[0x2a]	2898	1		T153	2		T53	4		T141	1
valid_sources[0x2b]	3425	1		T52	1		T23	1		T15	1
valid_sources[0x2c]	2797	1		T146	1		T58	10		T70	6
valid_sources[0x2d]	3188	1		T17	35		T140	3		T58	8
valid_sources[0x2e]	3249	1		T36	1		T146	2		T141	1
valid_sources[0x2f]	2588	1		T52	2		T54	1		T58	14
valid_sources[0x30]	3194	1		T11	2		T155	1		T58	9
valid_sources[0x31]	2453	1		T52	1		T56	1		T58	7
valid_sources[0x32]	2643	1		T11	1		T141	2		T58	12
valid_sources[0x33]	3385	1		T53	2		T58	15		T70	5
valid_sources[0x34]	4166	1		T13	1		T16	1		T143	3
valid_sources[0x35]	2487	1		T12	1		T24	5		T58	10
valid_sources[0x36]	2981	1		T26	1		T58	5		T70	1
valid_sources[0x37]	2514	1		T52	1		T14	2		T58	3
valid_sources[0x38]	2683	1		T52	2		T53	2		T58	10
valid_sources[0x39]	2795	1		T52	1		T15	1		T58	11
valid_sources[0x3a]	2786	1		T16	1		T153	2		T58	13
valid_sources[0x3b]	2804	1		T23	1		T124	3		T53	2
valid_sources[0x3c]	2878	1		T9	1		T52	2		T58	6
valid_sources[0x3d]	3076	1		T167	2		T58	12		T72	1
valid_sources[0x3e]	2517	1		T147	1		T58	6		T70	2
valid_sources[0x3f]	2623	1		T152	2		T58	16		T70	2
valid_sources[0x40]	3214	1		T144	3		T24	1		T58	6
valid_sources[0x41]	2935	1		T36	1		T143	1		T58	13
valid_sources[0x42]	2528	1		T55	2		T58	11		T71	9
valid_sources[0x43]	3235	1		T6	8		T23	1		T58	12
valid_sources[0x44]	2660	1		T124	2		T149	2		T58	8
valid_sources[0x45]	3985	1		T26	1		T168	10		T12	1
valid_sources[0x46]	3140	1		T13	3		T58	7		T70	1
valid_sources[0x47]	2507	1		T19	1		T36	1		T58	2
valid_sources[0x48]	2743	1		T4	9		T5	5		T11	1
valid_sources[0x49]	3454	1		T155	1		T141	1		T58	10
valid_sources[0x4a]	3035	1		T23	1		T58	10		T70	3
valid_sources[0x4b]	2629	1		T8	5		T11	1		T140	2
valid_sources[0x4c]	2999	1		T52	2		T24	2		T58	9
valid_sources[0x4d]	3414	1		T22	1		T141	1		T58	8
valid_sources[0x4e]	3381	1		T58	11		T70	1		T72	4
valid_sources[0x4f]	3097	1		T140	1		T58	4		T72	1
valid_sources[0x50]	2592	1		T13	4		T23	1		T149	1
valid_sources[0x51]	2871	1		T16	2		T151	6		T15	1
valid_sources[0x52]	3005	1		T52	1		T141	1		T58	9
valid_sources[0x53]	2838	1		T153	2		T58	6		T72	6
valid_sources[0x54]	2767	1		T21	3		T18	2		T141	1
valid_sources[0x55]	2979	1		T52	2		T56	1		T58	11
valid_sources[0x56]	2584	1		T52	1		T155	1		T143	1
valid_sources[0x57]	3144	1		T26	1		T52	1		T58	12
valid_sources[0x58]	2783	1		T35	2		T154	1		T58	12
valid_sources[0x59]	2453	1		T52	1		T24	2		T58	16
valid_sources[0x5a]	2920	1		T148	2		T152	1		T58	9
valid_sources[0x5b]	2678	1		T58	6		T70	1		T72	2
valid_sources[0x5c]	3774	1		T11	1		T169	1		T58	12
valid_sources[0x5d]	2990	1		T36	1		T52	1		T11	1
valid_sources[0x5e]	3016	1		T55	5		T23	1		T154	2
valid_sources[0x5f]	3092	1		T155	1		T58	7		T70	4
valid_sources[0x60]	2817	1		T23	2		T154	1		T58	16
valid_sources[0x61]	2846	1		T34	1		T23	2		T58	9
valid_sources[0x62]	3021	1		T36	3		T22	2		T58	15
valid_sources[0x63]	3178	1		T13	2		T166	5		T52	1
valid_sources[0x64]	3266	1		T58	10		T70	1		T72	5
valid_sources[0x65]	2884	1		T58	10		T70	2		T71	17
valid_sources[0x66]	3450	1		T16	1		T141	1		T58	14
valid_sources[0x67]	3235	1		T23	1		T58	9		T72	2
valid_sources[0x68]	2999	1		T140	1		T146	1		T58	9
valid_sources[0x69]	3214	1		T23	4		T58	8		T70	8
valid_sources[0x6a]	2952	1		T7	5		T52	1		T53	2
valid_sources[0x6b]	2445	1		T52	1		T149	1		T58	11
valid_sources[0x6c]	3622	1		T58	13		T70	1		T72	5
valid_sources[0x6d]	3234	1		T58	11		T70	6		T72	9
valid_sources[0x6e]	2761	1		T20	6		T24	1		T58	8
valid_sources[0x6f]	2799	1		T141	1		T58	12		T72	5
valid_sources[0x70]	2783	1		T16	1		T143	1		T169	4
valid_sources[0x71]	2463	1		T26	2		T52	1		T146	2
valid_sources[0x72]	3412	1		T26	1		T11	2		T53	2
valid_sources[0x73]	3106	1		T19	5		T52	1		T15	1
valid_sources[0x74]	2566	1		T52	1		T23	6		T58	7
valid_sources[0x75]	3052	1		T155	2		T58	14		T70	9
valid_sources[0x76]	3163	1		T16	1		T52	1		T151	8
valid_sources[0x77]	2791	1		T52	1		T54	1		T170	9
valid_sources[0x78]	2885	1		T52	1		T155	1		T56	2
valid_sources[0x79]	2600	1		T149	2		T58	16		T70	3
valid_sources[0x7a]	2954	1		T27	41		T58	13		T70	1
valid_sources[0x7b]	2726	1		T16	2		T140	1		T171	1
valid_sources[0x7c]	3052	1		T52	1		T11	1		T53	2
valid_sources[0x7d]	2728	1		T15	1		T149	1		T54	1
valid_sources[0x7e]	2746	1		T52	1		T24	1		T58	10
valid_sources[0x7f]	2955	1		T149	1		T58	16		T70	1
valid_sources[0x80]	3401	1		T23	3		T15	1		T58	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

275491

1

T7

2

T8

5

T4

4

values[0x0]

all_enables

biggest_size

136576

1

T7

1

T8

3

T9

1

values[0x1]

all_enables

biggest_size

136092

1

T7

1

T8

3

T9

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4377	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	26943	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9924	1		T58	442		T70	3		T72	3
values[0x0]	10554	1		T7	1		T37	2		T8	3
values[0x1]	10842	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3239	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	28081	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	200	1		T172	1		T58	8		T66	7
valid_sources[0x01]	112	1		T173	1		T172	1		T174	1
valid_sources[0x02]	109	1		T144	1		T133	1		T175	1
valid_sources[0x03]	95	1		T58	7		T68	2		T80	2
valid_sources[0x04]	84	1		T17	1		T176	1		T11	1
valid_sources[0x05]	295	1		T58	6		T79	1		T83	2
valid_sources[0x06]	95	1		T177	2		T178	1		T58	6
valid_sources[0x07]	73	1		T11	2		T172	1		T58	3
valid_sources[0x08]	104	1		T155	1		T58	9		T71	1
valid_sources[0x09]	119	1		T179	1		T58	10		T80	1
valid_sources[0x0a]	99	1		T180	1		T58	6		T80	1
valid_sources[0x0b]	82	1		T58	9		T80	2		T92	1
valid_sources[0x0c]	113	1		T181	1		T182	1		T175	1
valid_sources[0x0d]	141	1		T183	1		T184	11		T58	10
valid_sources[0x0e]	103	1		T58	8		T71	1		T80	2
valid_sources[0x0f]	106	1		T10	1		T185	1		T186	1
valid_sources[0x10]	125	1		T187	1		T188	1		T189	1
valid_sources[0x11]	82	1		T1	1		T37	1		T128	1
valid_sources[0x12]	98	1		T58	9		T80	2		T92	1
valid_sources[0x13]	97	1		T190	1		T21	1		T191	1
valid_sources[0x14]	99	1		T173	1		T58	9		T68	2
valid_sources[0x15]	135	1		T126	1		T192	1		T193	1
valid_sources[0x16]	110	1		T170	1		T58	4		T79	5
valid_sources[0x17]	110	1		T19	1		T11	3		T194	2
valid_sources[0x18]	161	1		T195	9		T27	5		T58	7
valid_sources[0x19]	87	1		T58	5		T69	5		T60	9
valid_sources[0x1a]	111	1		T181	1		T140	2		T155	1
valid_sources[0x1b]	103	1		T196	1		T197	1		T58	9
valid_sources[0x1c]	124	1		T198	1		T155	1		T199	1
valid_sources[0x1d]	96	1		T47	1		T58	4		T69	11
valid_sources[0x1e]	122	1		T200	1		T201	5		T202	1
valid_sources[0x1f]	139	1		T203	2		T204	3		T182	1
valid_sources[0x20]	111	1		T205	2		T58	1		T79	2
valid_sources[0x21]	92	1		T183	2		T176	2		T140	1
valid_sources[0x22]	89	1		T27	1		T58	12		T68	3
valid_sources[0x23]	93	1		T203	1		T155	1		T197	1
valid_sources[0x24]	90	1		T169	1		T57	1		T58	6
valid_sources[0x25]	116	1		T140	1		T58	6		T68	2
valid_sources[0x26]	99	1		T47	1		T176	1		T121	1
valid_sources[0x27]	117	1		T17	1		T155	1		T58	5
valid_sources[0x28]	124	1		T144	1		T185	1		T58	4
valid_sources[0x29]	93	1		T206	1		T140	2		T54	1
valid_sources[0x2a]	76	1		T203	1		T58	8		T80	1
valid_sources[0x2b]	117	1		T24	1		T58	11		T71	1
valid_sources[0x2c]	228	1		T35	2		T207	4		T208	1
valid_sources[0x2d]	238	1		T47	1		T204	4		T58	3
valid_sources[0x2e]	126	1		T55	2		T209	1		T127	1
valid_sources[0x2f]	203	1		T48	1		T210	11		T211	3
valid_sources[0x30]	114	1		T3	1		T16	1		T212	1
valid_sources[0x31]	93	1		T122	1		T127	1		T58	3
valid_sources[0x32]	95	1		T137	1		T58	10		T68	1
valid_sources[0x33]	270	1		T63	1		T121	1		T58	12
valid_sources[0x34]	202	1		T6	4		T209	1		T177	1
valid_sources[0x35]	100	1		T171	1		T58	7		T71	1
valid_sources[0x36]	128	1		T58	8		T80	1		T83	2
valid_sources[0x37]	107	1		T2	1		T35	1		T213	2
valid_sources[0x38]	139	1		T8	1		T63	1		T206	1
valid_sources[0x39]	97	1		T203	1		T58	5		T80	2
valid_sources[0x3a]	113	1		T58	8		T68	1		T79	5
valid_sources[0x3b]	196	1		T198	3		T205	1		T188	1
valid_sources[0x3c]	130	1		T16	1		T200	1		T214	6
valid_sources[0x3d]	178	1		T183	1		T125	1		T215	8
valid_sources[0x3e]	104	1		T198	1		T177	1		T58	2
valid_sources[0x3f]	94	1		T123	1		T58	7		T80	1
valid_sources[0x40]	92	1		T58	9		T79	1		T80	1
valid_sources[0x41]	132	1		T216	1		T129	1		T197	1
valid_sources[0x42]	80	1		T203	1		T15	1		T58	7
valid_sources[0x43]	74	1		T16	1		T127	1		T58	6
valid_sources[0x44]	77	1		T15	1		T217	1		T58	9
valid_sources[0x45]	91	1		T218	4		T147	1		T58	7
valid_sources[0x46]	132	1		T43	1		T35	1		T219	2
valid_sources[0x47]	87	1		T58	3		T68	6		T80	1
valid_sources[0x48]	163	1		T177	1		T58	7		T68	6
valid_sources[0x49]	97	1		T206	1		T176	1		T173	1
valid_sources[0x4a]	123	1		T183	1		T58	6		T67	7
valid_sources[0x4b]	105	1		T58	8		T66	15		T80	1
valid_sources[0x4c]	84	1		T185	1		T177	1		T220	1
valid_sources[0x4d]	82	1		T172	1		T58	8		T79	2
valid_sources[0x4e]	88	1		T58	4		T83	2		T60	12
valid_sources[0x4f]	67	1		T177	1		T221	1		T141	1
valid_sources[0x50]	135	1		T129	1		T58	7		T68	2
valid_sources[0x51]	104	1		T58	5		T79	1		T85	4
valid_sources[0x52]	101	1		T37	1		T58	6		T69	2
valid_sources[0x53]	103	1		T65	7		T36	1		T192	1
valid_sources[0x54]	136	1		T200	2		T129	1		T141	1
valid_sources[0x55]	191	1		T9	1		T140	1		T209	1
valid_sources[0x56]	129	1		T27	1		T222	1		T58	5
valid_sources[0x57]	75	1		T223	1		T198	1		T58	11
valid_sources[0x58]	109	1		T42	9		T186	1		T136	1
valid_sources[0x59]	120	1		T58	6		T59	24		T93	2
valid_sources[0x5a]	86	1		T175	1		T18	1		T170	1
valid_sources[0x5b]	113	1		T204	4		T185	1		T122	1
valid_sources[0x5c]	109	1		T16	1		T183	2		T58	7
valid_sources[0x5d]	148	1		T138	1		T58	5		T80	2
valid_sources[0x5e]	94	1		T224	8		T197	1		T58	7
valid_sources[0x5f]	91	1		T201	3		T58	9		T79	3
valid_sources[0x60]	131	1		T35	1		T58	7		T68	10
valid_sources[0x61]	230	1		T225	1		T144	1		T226	1
valid_sources[0x62]	117	1		T183	1		T227	2		T185	2
valid_sources[0x63]	112	1		T181	1		T153	3		T228	1
valid_sources[0x64]	97	1		T145	1		T226	1		T58	7
valid_sources[0x65]	350	1		T58	9		T71	1		T68	5
valid_sources[0x66]	197	1		T229	8		T209	1		T141	5
valid_sources[0x67]	99	1		T41	1		T193	1		T58	1
valid_sources[0x68]	66	1		T58	8		T79	2		T92	1
valid_sources[0x69]	86	1		T230	1		T173	1		T197	1
valid_sources[0x6a]	83	1		T176	1		T58	9		T68	2
valid_sources[0x6b]	90	1		T209	1		T58	4		T67	7
valid_sources[0x6c]	126	1		T192	1		T180	1		T155	1
valid_sources[0x6d]	96	1		T6	1		T40	1		T193	1
valid_sources[0x6e]	100	1		T16	1		T144	2		T134	8
valid_sources[0x6f]	99	1		T205	1		T182	1		T122	1
valid_sources[0x70]	121	1		T35	2		T209	1		T186	1
valid_sources[0x71]	92	1		T205	1		T168	1		T58	9
valid_sources[0x72]	91	1		T27	1		T192	1		T58	8
valid_sources[0x73]	123	1		T33	10		T58	3		T71	2
valid_sources[0x74]	90	1		T177	1		T220	1		T58	6
valid_sources[0x75]	87	1		T65	4		T188	1		T58	5
valid_sources[0x76]	95	1		T231	1		T147	2		T232	1
valid_sources[0x77]	155	1		T61	1		T58	7		T68	7
valid_sources[0x78]	117	1		T39	1		T233	1		T58	10
valid_sources[0x79]	224	1		T155	1		T18	1		T58	7
valid_sources[0x7a]	230	1		T210	3		T58	8		T68	14
valid_sources[0x7b]	309	1		T58	14		T68	2		T80	1
valid_sources[0x7c]	103	1		T191	2		T58	7		T72	1
valid_sources[0x7d]	101	1		T20	1		T155	1		T58	6
valid_sources[0x7e]	158	1		T7	1		T145	1		T146	7
valid_sources[0x7f]	109	1		T176	1		T182	1		T188	1
valid_sources[0x80]	93	1		T8	1		T227	1		T58	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7714

1

T58

423

T70

2

T72

3

values[0x0]

all_enables

biggest_size

9802

1

T7

1

T8

3

T28

3

values[0x1]

all_enables

biggest_size

9427

1

T1

2

T2

1

T3

1