Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	278625	1		T7	10		T8	23		T9	7
full_word	551319	1		T7	4		T8	11		T9	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	829664	1		T7	14		T8	34		T9	9
auto[TlIntgErrCmd]	97	1		T66	2		T67	9		T92	4
auto[TlIntgErrData]	92	1		T66	7		T67	5		T92	2
auto[TlIntgErrBoth]	91	1		T66	1		T67	6		T92	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	464225	1		T7	6		T8	7		T4	8
auto[1]	365719	1		T7	8		T8	27		T9	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	188248	1		T7	4		T8	2		T4	4
auto[TlIntgErrNone]	partial	auto[1]	90120	1		T7	6		T8	21		T9	7
auto[TlIntgErrNone]	full_word	auto[0]	275847	1		T7	2		T8	5		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	275449	1		T7	2		T8	6		T9	2
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T66	1		T67	2		T92	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T66	1		T67	6		T92	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T161	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T67	1		T119	1		T159	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T66	6		T67	2		T92	1
auto[TlIntgErrData]	partial	auto[1]	41	1		T66	1		T67	3		T92	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T94	1		T162	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T119	1		T159	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T67	2		T92	3		T93	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T66	1		T67	4		T92	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T119	1		T163	1		T158	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T94	1		T119	1		T164	1