Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	128893923	25283	0	0
late_debug_enable_rd_A	128893923	3445	0	0
late_debug_enable_regwen_rd_A	128893923	3189	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128893923	25283	0	0
T58	325344	1434	0	0
T59	501114	263	0	0
T66	112708	2	0	0
T67	193304	8	0	0
T68	26864	472	0	0
T69	12022	737	0	0
T79	139232	55	0	0
T80	16112	238	0	0
T81	65789	6	0	0
T92	44209	1	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128893923	3445	0	0
T58	325344	664	0	0
T59	501114	94	0	0
T67	193304	82	0	0
T68	26864	204	0	0
T80	16112	35	0	0
T88	5120	5	0	0
T90	39099	49	0	0
T93	47678	45	0	0
T119	143576	95	0	0
T120	26291	113	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128893923	3189	0	0
T58	325344	666	0	0
T59	501114	110	0	0
T67	193304	95	0	0
T68	26864	141	0	0
T80	16112	41	0	0
T88	5120	2	0	0
T90	39099	12	0	0
T93	47678	44	0	0
T119	143576	87	0	0
T120	26291	120	0	0