Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	46773691	4979396	0	0
MemTLResponseWithoutDebugIsError_A	46773691	4	0	0
NdmResetAckNeedsDebug_A	46773691	0	0	0
SbaTLRequestNeedsDebug_A	46773691	11875	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46773691	4979396	0	0
T4	30615	22646	0	0
T5	0	21894	0	0
T6	0	84235	0	0
T7	42849	19908	0	0
T8	397983	67523	0	0
T9	74939	71948	0	0
T10	30672	0	0	0
T13	0	24312	0	0
T19	0	100577	0	0
T28	134868	0	0	0
T30	3800	0	0	0
T34	4309	2881	0	0
T36	0	26798	0	0
T37	6175	0	0	0
T38	72391	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46773691	4	0	0
T5	120955	0	0	0
T6	145865	0	0	0
T13	182875	0	0	0
T31	96675	0	0	0
T39	8413	2	0	0
T40	0	2	0	0
T41	166651	0	0	0
T42	62360	0	0	0
T43	109145	0	0	0
T44	67383	0	0	0
T45	209467	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46773691	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46773691	11875	0	0
T1	16131	29	0	0
T2	241305	104	0	0
T3	512372	82	0	0
T4	30615	0	0	0
T7	42849	0	0	0
T8	397983	0	0	0
T9	74939	0	0	0
T10	30672	0	0	0
T28	134868	9	0	0
T29	0	15	0	0
T37	6175	0	0	0
T41	0	34	0	0
T46	0	113	0	0
T47	0	36	0	0
T48	0	123	0	0
T49	0	10	0	0