Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8695803 8694517 0 0
selKnown1 53109022 53107736 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8695803 8694517 0 0
T1 16354 16350 0 0
T2 23183 23179 0 0
T3 18901 18897 0 0
T4 2674 2670 0 0
T5 0 24 0 0
T7 5053 5049 0 0
T8 45411 45407 0 0
T9 15321 15317 0 0
T10 4121 4117 0 0
T28 17952 17948 0 0
T29 0 4 0 0
T37 292 288 0 0
T38 0 40 0 0
T42 0 16 0 0
T47 0 8 0 0
T64 0 40 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 53109022 53107736 0 0
T1 24310 24306 0 0
T2 252897 252893 0 0
T3 521823 521819 0 0
T4 31953 31949 0 0
T5 0 2 0 0
T7 45376 45372 0 0
T8 420688 420684 0 0
T9 82600 82596 0 0
T10 32728 32724 0 0
T28 143849 143845 0 0
T29 0 4 0 0
T37 6322 6318 0 0
T38 0 40 0 0
T42 0 16 0 0
T45 0 40 0 0
T47 0 8 0 0
T64 0 40 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2359780 2359568 0 0
selKnown1 46773691 46773479 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2359780 2359568 0 0
T1 8175 8174 0 0
T2 11590 11589 0 0
T3 9449 9448 0 0
T4 1336 1335 0 0
T7 2525 2524 0 0
T8 22699 22698 0 0
T9 7659 7658 0 0
T10 2054 2053 0 0
T28 8971 8970 0 0
T37 145 144 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 46773691 46773479 0 0
T1 16131 16130 0 0
T2 241305 241304 0 0
T3 512372 512371 0 0
T4 30615 30614 0 0
T7 42849 42848 0 0
T8 397983 397982 0 0
T9 74939 74938 0 0
T10 30672 30671 0 0
T28 134868 134867 0 0
T37 6175 6174 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 755 543 0 0
selKnown1 634 422 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 755 543 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 0 8 0 0
T7 1 0 0 0
T8 3 2 0 0
T9 1 0 0 0
T10 6 5 0 0
T28 5 4 0 0
T29 0 2 0 0
T37 1 0 0 0
T38 0 20 0 0
T42 0 8 0 0
T47 0 4 0 0
T64 0 20 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 634 422 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 0 1 0 0
T7 1 0 0 0
T8 3 2 0 0
T9 1 0 0 0
T10 1 0 0 0
T28 5 4 0 0
T29 0 2 0 0
T37 1 0 0 0
T38 0 20 0 0
T42 0 8 0 0
T45 0 20 0 0
T47 0 4 0 0
T64 0 20 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6333195 6332764 0 0
selKnown1 6332996 6332565 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6333195 6332764 0 0
T1 8175 8174 0 0
T2 11591 11590 0 0
T3 9450 9449 0 0
T4 1336 1335 0 0
T7 2526 2525 0 0
T8 22699 22698 0 0
T9 7660 7659 0 0
T10 2055 2054 0 0
T28 8971 8970 0 0
T37 145 144 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6332996 6332565 0 0
T1 8175 8174 0 0
T2 11590 11589 0 0
T3 9449 9448 0 0
T4 1336 1335 0 0
T7 2525 2524 0 0
T8 22699 22698 0 0
T9 7659 7658 0 0
T10 2054 2053 0 0
T28 8971 8970 0 0
T37 145 144 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2073 1642 0 0
selKnown1 1701 1270 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2073 1642 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 0 16 0 0
T7 1 0 0 0
T8 10 9 0 0
T9 1 0 0 0
T10 6 5 0 0
T28 5 4 0 0
T29 0 2 0 0
T37 1 0 0 0
T38 0 20 0 0
T42 0 8 0 0
T47 0 4 0 0
T64 0 20 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1701 1270 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 0 1 0 0
T7 1 0 0 0
T8 3 2 0 0
T9 1 0 0 0
T10 1 0 0 0
T28 5 4 0 0
T29 0 2 0 0
T37 1 0 0 0
T38 0 20 0 0
T42 0 8 0 0
T45 0 20 0 0
T47 0 4 0 0
T64 0 20 0 0

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