Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 192984 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 528227 1 T4 7 T34 80 T7 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 451320 1 T34 80 T7 1 T8 6
values[0x0] 132184 1 T4 13 T7 8 T6 2
values[0x1] 137707 1 T4 11 T7 7 T5 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 147040 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 574171 1 T4 7 T34 80 T7 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2874 1 T63 2 T65 13 T66 1
valid_sources[0x01] 3094 1 T63 2 T65 22 T67 10
valid_sources[0x02] 2728 1 T8 1 T63 5 T65 6
valid_sources[0x03] 2597 1 T8 1 T31 1 T15 1
valid_sources[0x04] 2399 1 T97 1 T18 2 T63 4
valid_sources[0x05] 2906 1 T30 1 T86 1 T97 2
valid_sources[0x06] 2853 1 T63 3 T65 19 T67 11
valid_sources[0x07] 2513 1 T97 2 T18 2 T38 32
valid_sources[0x08] 2783 1 T40 1 T63 2 T65 12
valid_sources[0x09] 3037 1 T14 3 T187 1 T15 1
valid_sources[0x0a] 2836 1 T164 4 T63 1 T65 8
valid_sources[0x0b] 2603 1 T7 1 T166 21 T63 4
valid_sources[0x0c] 2727 1 T40 1 T63 2 T65 7
valid_sources[0x0d] 2889 1 T10 1 T188 3 T63 1
valid_sources[0x0e] 2763 1 T15 1 T35 2 T63 3
valid_sources[0x0f] 2835 1 T30 1 T17 2 T63 5
valid_sources[0x10] 2946 1 T63 2 T65 8 T66 20
valid_sources[0x11] 2665 1 T63 3 T65 7 T66 14
valid_sources[0x12] 3195 1 T16 7 T31 1 T63 3
valid_sources[0x13] 2526 1 T8 1 T189 1 T65 4
valid_sources[0x14] 2875 1 T4 1 T65 9 T66 17
valid_sources[0x15] 2528 1 T9 1 T35 1 T65 19
valid_sources[0x16] 3145 1 T86 1 T10 1 T97 1
valid_sources[0x17] 2926 1 T8 1 T190 1 T35 1
valid_sources[0x18] 2812 1 T8 1 T191 2 T40 1
valid_sources[0x19] 2651 1 T160 1 T63 1 T65 19
valid_sources[0x1a] 2880 1 T63 3 T65 3 T67 14
valid_sources[0x1b] 2831 1 T74 1 T31 1 T63 2
valid_sources[0x1c] 3063 1 T65 9 T67 12 T60 11
valid_sources[0x1d] 3310 1 T19 3 T63 5 T65 8
valid_sources[0x1e] 2632 1 T15 1 T35 1 T65 11
valid_sources[0x1f] 2418 1 T5 1 T192 1 T63 2
valid_sources[0x20] 2695 1 T17 1 T35 5 T63 2
valid_sources[0x21] 2766 1 T8 3 T97 1 T15 1
valid_sources[0x22] 2407 1 T10 1 T192 3 T65 20
valid_sources[0x23] 2304 1 T8 1 T9 1 T10 5
valid_sources[0x24] 2761 1 T8 1 T9 1 T86 1
valid_sources[0x25] 3227 1 T7 1 T190 1 T63 3
valid_sources[0x26] 2713 1 T15 1 T63 5 T65 11
valid_sources[0x27] 2581 1 T8 1 T40 1 T63 4
valid_sources[0x28] 2415 1 T30 1 T97 1 T190 1
valid_sources[0x29] 3343 1 T9 1 T63 1 T65 15
valid_sources[0x2a] 2528 1 T10 1 T18 1 T15 1
valid_sources[0x2b] 2873 1 T4 2 T9 1 T86 1
valid_sources[0x2c] 2717 1 T65 10 T67 12 T60 14
valid_sources[0x2d] 2954 1 T35 2 T63 3 T65 5
valid_sources[0x2e] 2736 1 T7 1 T192 10 T63 2
valid_sources[0x2f] 2804 1 T8 1 T35 1 T63 2
valid_sources[0x30] 2729 1 T63 3 T65 4 T66 3
valid_sources[0x31] 2497 1 T63 3 T65 10 T67 9
valid_sources[0x32] 2729 1 T11 3 T65 18 T67 15
valid_sources[0x33] 2508 1 T8 1 T188 5 T20 2
valid_sources[0x34] 2690 1 T35 1 T63 2 T65 9
valid_sources[0x35] 2812 1 T187 1 T63 3 T65 3
valid_sources[0x36] 2472 1 T4 1 T63 1 T65 9
valid_sources[0x37] 2607 1 T19 1 T190 1 T63 4
valid_sources[0x38] 2547 1 T35 3 T63 2 T65 12
valid_sources[0x39] 3435 1 T4 1 T9 1 T191 2
valid_sources[0x3a] 3371 1 T4 1 T8 1 T63 1
valid_sources[0x3b] 2976 1 T30 1 T9 1 T15 1
valid_sources[0x3c] 2682 1 T63 3 T65 7 T67 8
valid_sources[0x3d] 2671 1 T30 1 T35 2 T63 2
valid_sources[0x3e] 2851 1 T63 2 T65 5 T66 10
valid_sources[0x3f] 3387 1 T86 2 T35 2 T63 3
valid_sources[0x40] 2767 1 T191 1 T63 2 T65 13
valid_sources[0x41] 2666 1 T18 1 T63 3 T65 4
valid_sources[0x42] 2657 1 T18 1 T65 3 T67 9
valid_sources[0x43] 2848 1 T30 1 T191 1 T63 3
valid_sources[0x44] 3117 1 T15 1 T63 5 T65 5
valid_sources[0x45] 2982 1 T23 1 T63 1 T65 15
valid_sources[0x46] 2872 1 T63 5 T65 13 T67 16
valid_sources[0x47] 2909 1 T86 1 T35 2 T63 1
valid_sources[0x48] 2688 1 T8 2 T31 2 T192 1
valid_sources[0x49] 2613 1 T10 2 T35 2 T65 5
valid_sources[0x4a] 2642 1 T191 4 T63 2 T65 4
valid_sources[0x4b] 2887 1 T8 1 T9 1 T86 1
valid_sources[0x4c] 2893 1 T4 1 T15 2 T23 2
valid_sources[0x4d] 3175 1 T190 1 T63 1 T65 19
valid_sources[0x4e] 2798 1 T187 1 T35 2 T20 2
valid_sources[0x4f] 2785 1 T191 1 T63 1 T65 7
valid_sources[0x50] 2767 1 T7 1 T21 1 T8 2
valid_sources[0x51] 3606 1 T4 1 T8 2 T86 1
valid_sources[0x52] 2843 1 T21 1 T65 11 T67 10
valid_sources[0x53] 2894 1 T63 5 T65 6 T67 15
valid_sources[0x54] 3051 1 T8 1 T192 1 T35 1
valid_sources[0x55] 2837 1 T7 1 T63 8 T65 5
valid_sources[0x56] 2561 1 T4 2 T187 1 T165 1
valid_sources[0x57] 2765 1 T23 1 T63 2 T65 22
valid_sources[0x58] 2767 1 T8 2 T63 3 T65 25
valid_sources[0x59] 2776 1 T7 1 T86 1 T10 1
valid_sources[0x5a] 3053 1 T192 1 T15 1 T63 5
valid_sources[0x5b] 2483 1 T35 1 T63 1 T65 6
valid_sources[0x5c] 2998 1 T16 2 T63 4 T65 10
valid_sources[0x5d] 2691 1 T15 1 T35 2 T63 1
valid_sources[0x5e] 2785 1 T8 1 T47 1 T35 2
valid_sources[0x5f] 2428 1 T9 1 T86 1 T97 1
valid_sources[0x60] 3162 1 T8 1 T86 1 T35 1
valid_sources[0x61] 2830 1 T18 1 T65 9 T67 13
valid_sources[0x62] 2784 1 T35 1 T63 5 T65 12
valid_sources[0x63] 2723 1 T30 1 T192 3 T63 1
valid_sources[0x64] 3311 1 T74 2 T9 1 T15 2
valid_sources[0x65] 2686 1 T160 3 T63 1 T65 11
valid_sources[0x66] 2588 1 T7 1 T148 1 T63 2
valid_sources[0x67] 2401 1 T63 2 T65 10 T67 11
valid_sources[0x68] 2540 1 T188 1 T63 7 T65 19
valid_sources[0x69] 2996 1 T8 1 T86 1 T65 19
valid_sources[0x6a] 2732 1 T9 1 T63 3 T65 14
valid_sources[0x6b] 2576 1 T35 1 T63 1 T65 9
valid_sources[0x6c] 2779 1 T8 1 T30 2 T97 2
valid_sources[0x6d] 3030 1 T86 1 T63 3 T65 18
valid_sources[0x6e] 2468 1 T8 1 T15 2 T35 3
valid_sources[0x6f] 2663 1 T74 1 T30 1 T9 2
valid_sources[0x70] 2888 1 T41 8 T63 4 T65 11
valid_sources[0x71] 2785 1 T15 2 T63 3 T65 12
valid_sources[0x72] 2893 1 T4 1 T65 12 T67 15
valid_sources[0x73] 2698 1 T98 24 T35 1 T63 1
valid_sources[0x74] 3429 1 T63 6 T65 5 T66 20
valid_sources[0x75] 2882 1 T63 1 T65 16 T66 7
valid_sources[0x76] 2899 1 T147 2 T63 7 T65 8
valid_sources[0x77] 2799 1 T9 1 T63 1 T65 7
valid_sources[0x78] 2919 1 T21 1 T8 1 T187 1
valid_sources[0x79] 2549 1 T9 2 T19 2 T63 2
valid_sources[0x7a] 3275 1 T7 1 T19 1 T63 2
valid_sources[0x7b] 2890 1 T4 1 T86 1 T10 1
valid_sources[0x7c] 2724 1 T30 1 T15 1 T24 2
valid_sources[0x7d] 2690 1 T63 3 T65 11 T67 9
valid_sources[0x7e] 3060 1 T8 1 T40 1 T15 1
valid_sources[0x7f] 2733 1 T17 2 T35 6 T65 12
valid_sources[0x80] 3120 1 T7 1 T65 18 T66 13



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 268117 1 T34 80 T8 4 T30 1
values[0x0] all_enables biggest_size 130299 1 T4 5 T7 4 T6 2
values[0x1] all_enables biggest_size 129811 1 T4 2 T6 2 T21 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5045 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 25656 1 T1 3 T2 3 T3 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 11291 1 T63 105 T65 11 T66 6
values[0x0] 9684 1 T1 1 T2 1 T3 1
values[0x1] 9726 1 T1 2 T2 2 T43 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3868 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 26833 1 T1 3 T2 3 T3 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 71 1 T159 1 T63 2 T62 3
valid_sources[0x01] 115 1 T75 4 T102 5 T64 3
valid_sources[0x02] 114 1 T86 1 T193 1 T98 2
valid_sources[0x03] 473 1 T194 1 T64 1 T61 1
valid_sources[0x04] 129 1 T195 1 T162 1 T63 2
valid_sources[0x05] 65 1 T165 1 T35 1 T63 1
valid_sources[0x06] 117 1 T150 1 T17 1 T63 2
valid_sources[0x07] 89 1 T45 2 T196 1 T187 1
valid_sources[0x08] 85 1 T43 1 T14 1 T67 1
valid_sources[0x09] 128 1 T98 1 T63 2 T64 1
valid_sources[0x0a] 91 1 T197 11 T80 1 T192 1
valid_sources[0x0b] 64 1 T63 2 T61 4 T62 1
valid_sources[0x0c] 105 1 T39 1 T63 2 T67 1
valid_sources[0x0d] 286 1 T86 1 T63 3 T95 2
valid_sources[0x0e] 70 1 T63 1 T65 1 T64 1
valid_sources[0x0f] 63 1 T43 2 T169 1 T63 2
valid_sources[0x10] 370 1 T143 1 T64 4 T92 1
valid_sources[0x11] 52 1 T198 2 T63 1 T67 2
valid_sources[0x12] 102 1 T36 1 T152 1 T199 1
valid_sources[0x13] 78 1 T63 1 T103 1 T64 4
valid_sources[0x14] 77 1 T86 1 T200 1 T52 2
valid_sources[0x15] 78 1 T201 2 T202 1 T114 1
valid_sources[0x16] 93 1 T68 17 T37 1 T143 2
valid_sources[0x17] 103 1 T17 1 T203 1 T204 1
valid_sources[0x18] 96 1 T205 1 T63 1 T100 21
valid_sources[0x19] 83 1 T192 1 T159 1 T63 3
valid_sources[0x1a] 78 1 T7 1 T8 2 T9 1
valid_sources[0x1b] 88 1 T25 2 T206 1 T163 2
valid_sources[0x1c] 167 1 T201 2 T207 1 T63 2
valid_sources[0x1d] 154 1 T106 1 T208 1 T48 1
valid_sources[0x1e] 100 1 T209 1 T63 2 T64 3
valid_sources[0x1f] 83 1 T3 1 T64 1 T95 3
valid_sources[0x20] 73 1 T84 1 T210 1 T63 2
valid_sources[0x21] 55 1 T2 1 T63 4 T67 1
valid_sources[0x22] 90 1 T211 1 T212 2 T63 3
valid_sources[0x23] 95 1 T145 1 T63 3 T64 1
valid_sources[0x24] 65 1 T39 1 T63 3 T64 2
valid_sources[0x25] 101 1 T63 1 T62 1 T91 4
valid_sources[0x26] 96 1 T64 6 T61 8 T62 3
valid_sources[0x27] 76 1 T27 1 T76 1 T80 1
valid_sources[0x28] 97 1 T9 1 T213 3 T168 1
valid_sources[0x29] 171 1 T10 1 T214 9 T55 1
valid_sources[0x2a] 62 1 T169 1 T13 1 T63 1
valid_sources[0x2b] 76 1 T63 6 T64 5 T90 2
valid_sources[0x2c] 110 1 T63 1 T93 15 T94 1
valid_sources[0x2d] 72 1 T43 1 T215 1 T52 1
valid_sources[0x2e] 66 1 T43 2 T10 1 T63 1
valid_sources[0x2f] 83 1 T169 1 T63 1 T64 2
valid_sources[0x30] 49 1 T188 1 T23 1 T63 1
valid_sources[0x31] 394 1 T200 1 T216 1 T63 2
valid_sources[0x32] 137 1 T217 4 T63 1 T64 2
valid_sources[0x33] 159 1 T188 1 T63 4 T64 1
valid_sources[0x34] 91 1 T106 2 T67 1 T64 2
valid_sources[0x35] 73 1 T17 1 T79 2 T218 1
valid_sources[0x36] 133 1 T219 2 T220 1 T148 1
valid_sources[0x37] 75 1 T221 2 T222 6 T144 1
valid_sources[0x38] 89 1 T63 3 T64 1 T94 1
valid_sources[0x39] 75 1 T98 2 T63 1 T64 4
valid_sources[0x3a] 85 1 T6 1 T169 1 T63 3
valid_sources[0x3b] 78 1 T106 1 T169 1 T165 1
valid_sources[0x3c] 93 1 T221 1 T219 2 T223 2
valid_sources[0x3d] 54 1 T73 1 T63 1 T64 5
valid_sources[0x3e] 139 1 T106 1 T143 1 T103 1
valid_sources[0x3f] 248 1 T29 2 T160 7 T63 1
valid_sources[0x40] 89 1 T188 1 T63 2 T66 2
valid_sources[0x41] 103 1 T165 1 T192 1 T166 1
valid_sources[0x42] 99 1 T45 2 T224 1 T63 3
valid_sources[0x43] 173 1 T225 10 T64 1 T61 1
valid_sources[0x44] 137 1 T4 2 T5 5 T226 3
valid_sources[0x45] 117 1 T161 1 T227 1 T63 1
valid_sources[0x46] 126 1 T223 1 T13 1 T20 1
valid_sources[0x47] 74 1 T83 3 T220 3 T154 1
valid_sources[0x48] 111 1 T59 7 T73 1 T15 1
valid_sources[0x49] 218 1 T63 3 T64 5 T93 3
valid_sources[0x4a] 69 1 T106 1 T63 5 T64 3
valid_sources[0x4b] 74 1 T215 1 T39 1 T153 1
valid_sources[0x4c] 63 1 T228 1 T63 4 T64 6
valid_sources[0x4d] 255 1 T106 1 T13 1 T63 3
valid_sources[0x4e] 78 1 T15 1 T229 1 T63 4
valid_sources[0x4f] 71 1 T13 1 T63 2 T64 1
valid_sources[0x50] 71 1 T43 1 T16 8 T230 1
valid_sources[0x51] 83 1 T231 1 T63 4 T64 2
valid_sources[0x52] 108 1 T140 1 T232 1 T103 1
valid_sources[0x53] 107 1 T221 1 T215 1 T17 1
valid_sources[0x54] 82 1 T233 1 T221 3 T170 1
valid_sources[0x55] 76 1 T229 5 T102 6 T64 2
valid_sources[0x56] 72 1 T63 1 T67 1 T64 3
valid_sources[0x57] 71 1 T6 2 T28 1 T234 5
valid_sources[0x58] 111 1 T11 1 T12 7 T67 1
valid_sources[0x59] 61 1 T86 1 T19 1 T42 1
valid_sources[0x5a] 128 1 T17 1 T143 2 T167 5
valid_sources[0x5b] 113 1 T195 1 T231 1 T63 4
valid_sources[0x5c] 117 1 T64 4 T62 1 T136 14
valid_sources[0x5d] 116 1 T11 1 T13 1 T235 6
valid_sources[0x5e] 111 1 T63 4 T64 2 T95 3
valid_sources[0x5f] 88 1 T44 1 T236 1 T64 1
valid_sources[0x60] 87 1 T106 1 T192 3 T202 1
valid_sources[0x61] 83 1 T30 1 T169 1 T63 3
valid_sources[0x62] 81 1 T191 1 T32 1 T231 1
valid_sources[0x63] 70 1 T64 3 T92 1 T94 2
valid_sources[0x64] 144 1 T215 2 T39 1 T63 5
valid_sources[0x65] 94 1 T215 1 T213 1 T216 1
valid_sources[0x66] 117 1 T200 3 T63 1 T103 1
valid_sources[0x67] 268 1 T195 3 T63 2 T64 2
valid_sources[0x68] 219 1 T198 3 T200 4 T63 1
valid_sources[0x69] 94 1 T57 4 T63 1 T64 2
valid_sources[0x6a] 72 1 T215 1 T63 2 T64 6
valid_sources[0x6b] 115 1 T237 1 T63 3 T62 1
valid_sources[0x6c] 82 1 T236 2 T63 1 T62 2
valid_sources[0x6d] 64 1 T4 2 T29 1 T188 1
valid_sources[0x6e] 77 1 T146 1 T159 1 T63 3
valid_sources[0x6f] 68 1 T140 3 T28 1 T236 1
valid_sources[0x70] 277 1 T237 4 T212 1 T166 1
valid_sources[0x71] 89 1 T1 3 T86 1 T231 1
valid_sources[0x72] 80 1 T72 1 T86 1 T210 2
valid_sources[0x73] 1031 1 T221 1 T238 6 T23 1
valid_sources[0x74] 71 1 T205 2 T63 2 T100 2
valid_sources[0x75] 95 1 T106 1 T9 1 T143 2
valid_sources[0x76] 83 1 T28 1 T98 1 T239 1
valid_sources[0x77] 87 1 T2 1 T8 1 T78 1
valid_sources[0x78] 83 1 T240 2 T55 2 T63 1
valid_sources[0x79] 68 1 T107 1 T195 2 T60 7
valid_sources[0x7a] 94 1 T43 1 T15 2 T63 1
valid_sources[0x7b] 82 1 T106 1 T18 1 T63 1
valid_sources[0x7c] 110 1 T221 1 T241 3 T15 1
valid_sources[0x7d] 71 1 T106 1 T242 4 T210 1
valid_sources[0x7e] 144 1 T223 1 T243 8 T63 3
valid_sources[0x7f] 106 1 T161 1 T202 1 T63 1
valid_sources[0x80] 95 1 T215 1 T226 3 T60 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 8159 1 T63 95 T65 11 T66 3
values[0x0] all_enables biggest_size 8992 1 T1 1 T2 1 T3 1
values[0x1] all_enables biggest_size 8505 1 T1 2 T2 2 T43 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%