SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 747371 | 1 | T4 | 24 | T7 | 16 | T5 | 1 | |||
auto[1] | 26563 | 1 | T34 | 80 | T35 | 80 | T63 | 646 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 773753 | 1 | T4 | 24 | T34 | 80 | T7 | 16 | |||
values[1] | 18 | 1 | T91 | 1 | T108 | 2 | T174 | 1 | |||
values[2] | 1 | 1 | T175 | 1 | - | - | - | - | |||
values[3] | 92 | 1 | T60 | 3 | T62 | 8 | T91 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 773760 | 1 | T4 | 24 | T34 | 80 | T7 | 16 | |||
values[1] | 19 | 1 | T60 | 1 | T62 | 1 | T176 | 1 | |||
values[2] | 3 | 1 | T62 | 1 | T108 | 1 | T177 | 1 | |||
values[3] | 75 | 1 | T60 | 2 | T62 | 7 | T91 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 773674 | 1 | T4 | 24 | T34 | 80 | T7 | 16 | |||
auto[TlIntgErrCmd] | 86 | 1 | T60 | 2 | T62 | 5 | T91 | 5 | |||
auto[TlIntgErrData] | 79 | 1 | T60 | 5 | T62 | 7 | T91 | 3 | |||
auto[TlIntgErrBoth] | 95 | 1 | T60 | 3 | T62 | 8 | T91 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 53769 | 0 | T1 | 3 | T2 | 3 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53587 | 1 | T1 | 3 | T2 | 3 | T3 | 1 | |||
values[1] | 21 | 1 | T60 | 2 | T62 | 4 | T93 | 1 | |||
values[2] | 9 | 1 | T91 | 1 | T176 | 1 | T108 | 1 | |||
values[3] | 93 | 1 | T60 | 4 | T62 | 4 | T91 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53596 | 1 | T1 | 3 | T2 | 3 | T3 | 1 | |||
values[1] | 23 | 1 | T60 | 1 | T62 | 3 | T93 | 1 | |||
values[2] | 3 | 1 | T178 | 1 | T179 | 1 | T180 | 1 | |||
values[3] | 84 | 1 | T60 | 3 | T62 | 6 | T91 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 53509 | 1 | T1 | 3 | T2 | 3 | T3 | 1 | |||
auto[TlIntgErrCmd] | 87 | 1 | T60 | 3 | T62 | 6 | T91 | 2 | |||
auto[TlIntgErrData] | 78 | 1 | T60 | 1 | T62 | 6 | T91 | 3 | |||
auto[TlIntgErrBoth] | 95 | 1 | T60 | 6 | T62 | 8 | T91 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |